Commit be547111 authored by Bhawanpreet Lakha's avatar Bhawanpreet Lakha Committed by Alex Deucher
Browse files

drm/amd/display: Add DCN3 DIO 



Add support for the DIO (Display IO)  block of DCN3, which entails our
stream and link encoders.

HW Blocks:

    +--------+
    |  DIO   |
    +--------+

Signed-off-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7c40270b

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+14 −0
Original line number Diff line number Diff line
@@ -3133,6 +3133,11 @@ void core_link_enable_stream( 


	pipe_ctx->stream->link->link_state_valid = true;



#if defined(CONFIG_DRM_AMD_DC_DCN3_0)

		if (pipe_ctx->stream_res.tg->funcs->set_out_mux)

					pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO);

#endif



	if (dc_is_dvi_signal(pipe_ctx->stream->signal))

		pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(

			pipe_ctx->stream_res.stream_enc,
@@ -3215,6 +3220,15 @@ void core_link_enable_stream( 
					CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,

					COLOR_DEPTH_UNDEFINED);



		/* This second call is needed to reconfigure the DIG

		 * as a workaround for the incorrect value being applied

		 * from transmitter control.

		 */

		if (!dc_is_virtual_signal(pipe_ctx->stream->signal))

			stream->link->link_enc->funcs->setup(

				stream->link->link_enc,

				pipe_ctx->stream->signal);



		dc->hwss.enable_stream(pipe_ctx);



		/* Set DPS PPS SDP (AKA "info frames") */

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

+6 −0
Original line number Diff line number Diff line
@@ -153,6 +153,12 @@ struct dcn10_link_enc_registers { 
	uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3;

	uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2;

	uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3;

#if defined(CONFIG_DRM_AMD_DC_DCN3_0)

	uint32_t TMDS_DCBALANCER_CONTROL;

	uint32_t PHYA_LINK_CNTL2;

	uint32_t PHYB_LINK_CNTL2;

	uint32_t PHYC_LINK_CNTL2;

#endif

};



#define LE_SF(reg_name, field_name, post_fix)\

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

+42 −0
Original line number Diff line number Diff line
@@ -169,6 +169,14 @@ struct dcn10_stream_enc_registers { 
	uint32_t DP_SEC_METADATA_TRANSMISSION;

	uint32_t HDMI_METADATA_PACKET_CONTROL;

	uint32_t DP_SEC_FRAMING4;

#if defined(CONFIG_DRM_AMD_DC_DCN3_0)

	uint32_t DP_GSP11_CNTL;

	uint32_t HDMI_GENERIC_PACKET_CONTROL6;

	uint32_t HDMI_GENERIC_PACKET_CONTROL7;

	uint32_t HDMI_GENERIC_PACKET_CONTROL8;

	uint32_t HDMI_GENERIC_PACKET_CONTROL9;

	uint32_t HDMI_GENERIC_PACKET_CONTROL10;

#endif

	uint32_t DIG_CLOCK_PATTERN;

};
@@ -483,14 +491,48 @@ struct dcn10_stream_enc_registers { 
	type DP_PIXEL_COMBINE;\

	type DP_SST_SDP_SPLITTING



#if defined(CONFIG_DRM_AMD_DC_DCN3_0)

#define SE_REG_FIELD_LIST_DCN3_0(type) \

	type HDMI_GENERIC8_CONT;\

	type HDMI_GENERIC8_SEND;\

	type HDMI_GENERIC8_LINE;\

	type HDMI_GENERIC9_CONT;\

	type HDMI_GENERIC9_SEND;\

	type HDMI_GENERIC9_LINE;\

	type HDMI_GENERIC10_CONT;\

	type HDMI_GENERIC10_SEND;\

	type HDMI_GENERIC10_LINE;\

	type HDMI_GENERIC11_CONT;\

	type HDMI_GENERIC11_SEND;\

	type HDMI_GENERIC11_LINE;\

	type HDMI_GENERIC12_CONT;\

	type HDMI_GENERIC12_SEND;\

	type HDMI_GENERIC12_LINE;\

	type HDMI_GENERIC13_CONT;\

	type HDMI_GENERIC13_SEND;\

	type HDMI_GENERIC13_LINE;\

	type HDMI_GENERIC14_CONT;\

	type HDMI_GENERIC14_SEND;\

	type HDMI_GENERIC14_LINE;\

	type DP_SEC_GSP11_PPS;\

	type DP_SEC_GSP11_ENABLE;\

	type DP_SEC_GSP11_LINE_NUM

#endif



struct dcn10_stream_encoder_shift {

	SE_REG_FIELD_LIST_DCN1_0(uint8_t);

	SE_REG_FIELD_LIST_DCN2_0(uint8_t);

#if defined(CONFIG_DRM_AMD_DC_DCN3_0)

	SE_REG_FIELD_LIST_DCN3_0(uint8_t);

#endif

};



struct dcn10_stream_encoder_mask {

	SE_REG_FIELD_LIST_DCN1_0(uint32_t);

	SE_REG_FIELD_LIST_DCN2_0(uint32_t);

#if defined(CONFIG_DRM_AMD_DC_DCN3_0)

	SE_REG_FIELD_LIST_DCN3_0(uint32_t);

#endif

};



struct dcn10_stream_encoder {

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h

+4 −0
Original line number Diff line number Diff line
@@ -274,6 +274,10 @@ struct mpll_cfg { 
	bool dp_tx1_vergdrv_byp;

	bool dp_tx2_vergdrv_byp;

	bool dp_tx3_vergdrv_byp;

#if defined(CONFIG_DRM_AMD_DC_DCN3_0)

	uint32_t tx_peaking_lvl;

	uint32_t ctr_reqs_pll;

#endif





};

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.c

0 → 100644
+205 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2020 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: AMD

 *

 */



#include "reg_helper.h"



#include "core_types.h"

#include "link_encoder.h"

#include "dcn30_dio_link_encoder.h"

#include "stream_encoder.h"

#include "i2caux_interface.h"

#include "dc_bios_types.h"

/* #include "dcn3ag/dcn3ag_phy_fw.h" */



#include "gpio_service_interface.h"



#define CTX \

	enc10->base.ctx

#define DC_LOGGER \

	enc10->base.ctx->logger



#define REG(reg)\

	(enc10->link_regs->reg)



#undef FN

#define FN(reg_name, field_name) \

	enc10->link_shift->field_name, enc10->link_mask->field_name



#define IND_REG(index) \

	(enc10->link_regs->index)





static bool dcn30_link_encoder_validate_output_with_stream(

	struct link_encoder *enc,

	const struct dc_stream_state *stream)

{

		return dcn10_link_encoder_validate_output_with_stream(enc, stream);

}



static const struct link_encoder_funcs dcn30_link_enc_funcs = {

	.read_state = link_enc2_read_state,

	.validate_output_with_stream =

			dcn30_link_encoder_validate_output_with_stream,

	.hw_init = enc2_hw_init,

	.setup = dcn10_link_encoder_setup,

	.enable_tmds_output = dcn10_link_encoder_enable_tmds_output,

	.enable_dp_output = dcn20_link_encoder_enable_dp_output,

	.enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,

	.disable_output = dcn10_link_encoder_disable_output,

	.dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,

	.dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,

	.update_mst_stream_allocation_table =

		dcn10_link_encoder_update_mst_stream_allocation_table,

	.psr_program_dp_dphy_fast_training =

			dcn10_psr_program_dp_dphy_fast_training,

	.psr_program_secondary_packet = dcn10_psr_program_secondary_packet,

	.connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,

	.enable_hpd = dcn10_link_encoder_enable_hpd,

	.disable_hpd = dcn10_link_encoder_disable_hpd,

	.is_dig_enabled = dcn10_is_dig_enabled,

	.destroy = dcn10_link_encoder_destroy,

	.fec_set_enable = enc2_fec_set_enable,

	.fec_set_ready = enc2_fec_set_ready,

	.fec_is_active = enc2_fec_is_active,

	.get_dig_frontend = dcn10_get_dig_frontend,

	.get_dig_mode = dcn10_get_dig_mode,

	.is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,

	.get_max_link_cap = dcn20_link_encoder_get_max_link_cap,

};



void dcn30_link_encoder_construct(

	struct dcn20_link_encoder *enc20,

	const struct encoder_init_data *init_data,

	const struct encoder_feature_support *enc_features,

	const struct dcn10_link_enc_registers *link_regs,

	const struct dcn10_link_enc_aux_registers *aux_regs,

	const struct dcn10_link_enc_hpd_registers *hpd_regs,

	const struct dcn10_link_enc_shift *link_shift,

	const struct dcn10_link_enc_mask *link_mask)

{

	struct bp_encoder_cap_info bp_cap_info = {0};

	const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;

	enum bp_result result = BP_RESULT_OK;

	struct dcn10_link_encoder *enc10 = &enc20->enc10;



	enc10->base.funcs = &dcn30_link_enc_funcs;

	enc10->base.ctx = init_data->ctx;

	enc10->base.id = init_data->encoder;



	enc10->base.hpd_source = init_data->hpd_source;

	enc10->base.connector = init_data->connector;



	enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;



	enc10->base.features = *enc_features;



	enc10->base.transmitter = init_data->transmitter;



	/* set the flag to indicate whether driver poll the I2C data pin

	 * while doing the DP sink detect

	 */



/*	if (dal_adapter_service_is_feature_supported(as,

		FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))

		enc10->base.features.flags.bits.

			DP_SINK_DETECT_POLL_DATA_PIN = true;*/



	enc10->base.output_signals =

		SIGNAL_TYPE_DVI_SINGLE_LINK |

		SIGNAL_TYPE_DVI_DUAL_LINK |

		SIGNAL_TYPE_LVDS |

		SIGNAL_TYPE_DISPLAY_PORT |

		SIGNAL_TYPE_DISPLAY_PORT_MST |

		SIGNAL_TYPE_EDP |

		SIGNAL_TYPE_HDMI_TYPE_A;



	/* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.

	 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.

	 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer

	 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.

	 * Prefer DIG assignment is decided by board design.

	 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design

	 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.

	 * By this, adding DIGG should not hurt DCE 8.0.

	 * This will let DCE 8.1 share DCE 8.0 as much as possible

	 */



	enc10->link_regs = link_regs;

	enc10->aux_regs = aux_regs;

	enc10->hpd_regs = hpd_regs;

	enc10->link_shift = link_shift;

	enc10->link_mask = link_mask;



	switch (enc10->base.transmitter) {

	case TRANSMITTER_UNIPHY_A:

		enc10->base.preferred_engine = ENGINE_ID_DIGA;

	break;

	case TRANSMITTER_UNIPHY_B:

		enc10->base.preferred_engine = ENGINE_ID_DIGB;

	break;

	case TRANSMITTER_UNIPHY_C:

		enc10->base.preferred_engine = ENGINE_ID_DIGC;

	break;

	case TRANSMITTER_UNIPHY_D:

		enc10->base.preferred_engine = ENGINE_ID_DIGD;

	break;

	case TRANSMITTER_UNIPHY_E:

		enc10->base.preferred_engine = ENGINE_ID_DIGE;

	break;

	case TRANSMITTER_UNIPHY_F:

		enc10->base.preferred_engine = ENGINE_ID_DIGF;

	break;

	case TRANSMITTER_UNIPHY_G:

		enc10->base.preferred_engine = ENGINE_ID_DIGG;

	break;

	default:

		ASSERT_CRITICAL(false);

		enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;

	}



	/* default to one to mirror Windows behavior */

	enc10->base.features.flags.bits.HDMI_6GB_EN = 1;



	result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,

						enc10->base.id, &bp_cap_info);



	/* Override features with DCE-specific values */

	if (result == BP_RESULT_OK) {

		enc10->base.features.flags.bits.IS_HBR2_CAPABLE =

				bp_cap_info.DP_HBR2_EN;

		enc10->base.features.flags.bits.IS_HBR3_CAPABLE =

				bp_cap_info.DP_HBR3_EN;

		enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;

		enc10->base.features.flags.bits.DP_IS_USB_C =

				bp_cap_info.DP_IS_USB_C;

	} else {

		DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",

				__func__,

				result);

	}

	if (enc10->base.ctx->dc->debug.hdmi20_disable) {

		enc10->base.features.flags.bits.HDMI_6GB_EN = 0;

	}

}