Commit be2d3ece authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'perf-tools-for-v5.18-2022-04-02' of... 

Merge tag 'perf-tools-for-v5.18-2022-04-02' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux

Pull more perf tools updates from Arnaldo Carvalho de Melo:

 - Avoid SEGV if core.cpus isn't set in 'perf stat'.

 - Stop depending on .git files for building PERF-VERSION-FILE, used in
   'perf --version', fixing some perf tools build scenarios.

 - Convert tracepoint.py example to python3.

 - Update UAPI header copies from the kernel sources: socket,
   mman-common, msr-index, KVM, i915 and cpufeatures.

 - Update copy of libbpf's hashmap.c.

 - Directly return instead of using local ret variable in
   evlist__create_syswide_maps(), found by coccinelle.

* tag 'perf-tools-for-v5.18-2022-04-02' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux:
  perf python: Convert tracepoint.py example to python3
  perf evlist: Directly return instead of using local ret variable
  perf cpumap: More cpu map reuse by merge.
  perf cpumap: Add is_subset function
  perf evlist: Rename cpus to user_requested_cpus
  perf tools: Stop depending on .git files for building PERF-VERSION-FILE
  tools headers cpufeatures: Sync with the kernel sources
  tools headers UAPI: Sync drm/i915_drm.h with the kernel sources
  tools headers UAPI: Sync linux/kvm.h with the kernel sources
  tools kvm headers arm64: Update KVM headers from the kernel sources
  tools arch x86: Sync the msr-index.h copy with the kernel sources
  tools headers UAPI: Sync asm-generic/mman-common.h with the kernel
  perf beauty: Update copy of linux/socket.h with the kernel sources
  perf tools: Update copy of libbpf's hashmap.c
  perf stat: Avoid SEGV if core.cpus isn't set
parents d897b680 7e2022af

tools/arch/arm64/include/uapi/asm/kvm.h

+10 −0
Original line number Original line Diff line number Diff line
@@ -419,6 +419,16 @@ struct kvm_arm_copy_mte_tags { 
#define KVM_PSCI_RET_INVAL		PSCI_RET_INVALID_PARAMS

#define KVM_PSCI_RET_INVAL		PSCI_RET_INVALID_PARAMS

#define KVM_PSCI_RET_DENIED		PSCI_RET_DENIED

#define KVM_PSCI_RET_DENIED		PSCI_RET_DENIED





/* arm64-specific kvm_run::system_event flags */

/*

 * Reset caused by a PSCI v1.1 SYSTEM_RESET2 call.

 * Valid only when the system event has a type of KVM_SYSTEM_EVENT_RESET.

 */

#define KVM_SYSTEM_EVENT_RESET_FLAG_PSCI_RESET2	(1ULL << 0)



/* run->fail_entry.hardware_entry_failure_reason codes. */

#define KVM_EXIT_FAIL_ENTRY_CPU_UNSUPPORTED	(1ULL << 0)



#endif

#endif





#endif /* __ARM_KVM_H__ */
 
#endif /* __ARM_KVM_H__ */

tools/arch/x86/include/asm/cpufeatures.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -388,6 +388,7 @@ 
#define X86_FEATURE_TSXLDTRK		(18*32+16) /* TSX Suspend Load Address Tracking */

#define X86_FEATURE_TSXLDTRK		(18*32+16) /* TSX Suspend Load Address Tracking */

#define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */

#define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */

#define X86_FEATURE_ARCH_LBR		(18*32+19) /* Intel ARCH LBR */

#define X86_FEATURE_ARCH_LBR		(18*32+19) /* Intel ARCH LBR */

#define X86_FEATURE_IBT			(18*32+20) /* Indirect Branch Tracking */

#define X86_FEATURE_AMX_BF16		(18*32+22) /* AMX bf16 Support */

#define X86_FEATURE_AMX_BF16		(18*32+22) /* AMX bf16 Support */

#define X86_FEATURE_AVX512_FP16		(18*32+23) /* AVX512 FP16 */

#define X86_FEATURE_AVX512_FP16		(18*32+23) /* AVX512 FP16 */

#define X86_FEATURE_AMX_TILE		(18*32+24) /* AMX tile Support */

#define X86_FEATURE_AMX_TILE		(18*32+24) /* AMX tile Support */

tools/arch/x86/include/asm/msr-index.h

+21 −1
Original line number Original line Diff line number Diff line
@@ -205,6 +205,8 @@ 
#define RTIT_CTL_DISRETC		BIT(11)

#define RTIT_CTL_DISRETC		BIT(11)

#define RTIT_CTL_PTW_EN			BIT(12)

#define RTIT_CTL_PTW_EN			BIT(12)

#define RTIT_CTL_BRANCH_EN		BIT(13)

#define RTIT_CTL_BRANCH_EN		BIT(13)

#define RTIT_CTL_EVENT_EN		BIT(31)

#define RTIT_CTL_NOTNT			BIT_ULL(55)

#define RTIT_CTL_MTC_RANGE_OFFSET	14

#define RTIT_CTL_MTC_RANGE_OFFSET	14

#define RTIT_CTL_MTC_RANGE		(0x0full << RTIT_CTL_MTC_RANGE_OFFSET)

#define RTIT_CTL_MTC_RANGE		(0x0full << RTIT_CTL_MTC_RANGE_OFFSET)

#define RTIT_CTL_CYC_THRESH_OFFSET	19

#define RTIT_CTL_CYC_THRESH_OFFSET	19
@@ -360,11 +362,29 @@ 
#define MSR_ATOM_CORE_TURBO_RATIOS	0x0000066c

#define MSR_ATOM_CORE_TURBO_RATIOS	0x0000066c

#define MSR_ATOM_CORE_TURBO_VIDS	0x0000066d

#define MSR_ATOM_CORE_TURBO_VIDS	0x0000066d







#define MSR_CORE_PERF_LIMIT_REASONS	0x00000690

#define MSR_CORE_PERF_LIMIT_REASONS	0x00000690

#define MSR_GFX_PERF_LIMIT_REASONS	0x000006B0

#define MSR_GFX_PERF_LIMIT_REASONS	0x000006B0

#define MSR_RING_PERF_LIMIT_REASONS	0x000006B1

#define MSR_RING_PERF_LIMIT_REASONS	0x000006B1





/* Control-flow Enforcement Technology MSRs */

#define MSR_IA32_U_CET			0x000006a0 /* user mode cet */

#define MSR_IA32_S_CET			0x000006a2 /* kernel mode cet */

#define CET_SHSTK_EN			BIT_ULL(0)

#define CET_WRSS_EN			BIT_ULL(1)

#define CET_ENDBR_EN			BIT_ULL(2)

#define CET_LEG_IW_EN			BIT_ULL(3)

#define CET_NO_TRACK_EN			BIT_ULL(4)

#define CET_SUPPRESS_DISABLE		BIT_ULL(5)

#define CET_RESERVED			(BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9))

#define CET_SUPPRESS			BIT_ULL(10)

#define CET_WAIT_ENDBR			BIT_ULL(11)



#define MSR_IA32_PL0_SSP		0x000006a4 /* ring-0 shadow stack pointer */

#define MSR_IA32_PL1_SSP		0x000006a5 /* ring-1 shadow stack pointer */

#define MSR_IA32_PL2_SSP		0x000006a6 /* ring-2 shadow stack pointer */

#define MSR_IA32_PL3_SSP		0x000006a7 /* ring-3 shadow stack pointer */

#define MSR_IA32_INT_SSP_TAB		0x000006a8 /* exception shadow stack table */



/* Hardware P state interface */

/* Hardware P state interface */

#define MSR_PPERF			0x0000064e

#define MSR_PPERF			0x0000064e

#define MSR_PERF_LIMIT_REASONS		0x0000064f

#define MSR_PERF_LIMIT_REASONS		0x0000064f

tools/include/uapi/asm-generic/mman-common.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -75,6 +75,8 @@ 
#define MADV_POPULATE_READ	22	/* populate (prefault) page tables readable */

#define MADV_POPULATE_READ	22	/* populate (prefault) page tables readable */

#define MADV_POPULATE_WRITE	23	/* populate (prefault) page tables writable */

#define MADV_POPULATE_WRITE	23	/* populate (prefault) page tables writable */





#define MADV_DONTNEED_LOCKED	24	/* like DONTNEED, but drop locked pages too */



/* compatibility flags */

/* compatibility flags */

#define MAP_FILE	0

#define MAP_FILE	0

tools/include/uapi/drm/i915_drm.h

+40 −5
Original line number Original line Diff line number Diff line
@@ -1118,10 +1118,16 @@ struct drm_i915_gem_exec_object2 { 
	/**

	/**

	 * When the EXEC_OBJECT_PINNED flag is specified this is populated by

	 * When the EXEC_OBJECT_PINNED flag is specified this is populated by

	 * the user with the GTT offset at which this object will be pinned.

	 * the user with the GTT offset at which this object will be pinned.

	 *

	 * When the I915_EXEC_NO_RELOC flag is specified this must contain the

	 * When the I915_EXEC_NO_RELOC flag is specified this must contain the

	 * presumed_offset of the object.

	 * presumed_offset of the object.

	 *

	 * During execbuffer2 the kernel populates it with the value of the

	 * During execbuffer2 the kernel populates it with the value of the

	 * current GTT offset of the object, for future presumed_offset writes.

	 * current GTT offset of the object, for future presumed_offset writes.

	 *

	 * See struct drm_i915_gem_create_ext for the rules when dealing with

	 * alignment restrictions with I915_MEMORY_CLASS_DEVICE, on devices with

	 * minimum page sizes, like DG2.

	 */

	 */

	__u64 offset;

	__u64 offset;
@@ -3144,11 +3150,40 @@ struct drm_i915_gem_create_ext { 
	 *

	 *

	 * The (page-aligned) allocated size for the object will be returned.

	 * The (page-aligned) allocated size for the object will be returned.

	 *

	 *

	 * Note that for some devices we have might have further minimum

	 *

	 * page-size restrictions(larger than 4K), like for device local-memory.

	 * DG2 64K min page size implications:

	 * However in general the final size here should always reflect any

	 *

	 * rounding up, if for example using the I915_GEM_CREATE_EXT_MEMORY_REGIONS

	 * On discrete platforms, starting from DG2, we have to contend with GTT

	 * extension to place the object in device local-memory.

	 * page size restrictions when dealing with I915_MEMORY_CLASS_DEVICE

	 * objects.  Specifically the hardware only supports 64K or larger GTT

	 * page sizes for such memory. The kernel will already ensure that all

	 * I915_MEMORY_CLASS_DEVICE memory is allocated using 64K or larger page

	 * sizes underneath.

	 *

	 * Note that the returned size here will always reflect any required

	 * rounding up done by the kernel, i.e 4K will now become 64K on devices

	 * such as DG2.

	 *

	 * Special DG2 GTT address alignment requirement:

	 *

	 * The GTT alignment will also need to be at least 2M for such objects.

	 *

	 * Note that due to how the hardware implements 64K GTT page support, we

	 * have some further complications:

	 *

	 *   1) The entire PDE (which covers a 2MB virtual address range), must

	 *   contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same

	 *   PDE is forbidden by the hardware.

	 *

	 *   2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM

	 *   objects.

	 *

	 * To keep things simple for userland, we mandate that any GTT mappings

	 * must be aligned to and rounded up to 2MB. The kernel will internally

	 * pad them out to the next 2MB boundary. As this only wastes virtual

	 * address space and avoids userland having to copy any needlessly

	 * complicated PDE sharing scheme (coloring) and only affects DG2, this

	 * is deemed to be a good compromise.

	 */

	 */

	__u64 size;

	__u64 size;

	/**

	/**