Commit be0ddf52 authored by Mark Brown's avatar Mark Brown Committed by Marc Zyngier
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arm64: booting: Document our requirements for fine grained traps with SME 



With SME we require that fine grained traps on access to TPIDR2_EL0 and
SMPRI_EL1 are disabled but did not document that fact. Add the relevant
register bits.

Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Reviewed-by: default avatarOliver Upton <oliver.upton@linux.dev>
Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20221101112716.52035-2-broonie@kernel.org
parent 4151bb63

Documentation/arm64/booting.rst

+8 −0
Original line number Diff line number Diff line
@@ -340,6 +340,14 @@ Before jumping into the kernel, the following conditions must be met: 
    - SMCR_EL2.LEN must be initialised to the same value for all CPUs the

      kernel will execute on.



    - HWFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.



    - HWFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.



    - HWFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.



    - HWFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.



  For CPUs with the Scalable Matrix Extension FA64 feature (FEAT_SME_FA64)



  - If EL3 is present: