Commit bd9289c5 authored by Zhen Lei's avatar Zhen Lei Committed by Yuntao Liu
Browse files

ARM: LPAE: Use phys_addr_t instead of unsigned long in outercache hooks 

hulk inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I8Q90B


CVE: NA

-------------------------------------------------------------------------

The outercache of some Hisilicon SOCs support physical addresses wider
than 32-bits. The unsigned long datatype is not sufficient for mapping
physical addresses >= 4GB. The commit ad6b9c9d ("ARM: 6671/1: LPAE:
use phys_addr_t instead of unsigned long in outercache functions") has
already modified the outercache functions. But the parameters of the
outercache hooks are not changed. This patch use phys_addr_t instead of
unsigned long in outercache hooks: inv_range, clean_range, flush_range.

To ensure the outercache that does not support LPAE works properly, do
cast phys_addr_t to unsigned long by adding a group of temporary
variables. For example:
-static void l2c220_inv_range(unsigned long start, unsigned long end)
+static void l2c220_inv_range(phys_addr_t pa_start, phys_addr_t pa_end)
 {
+	unsigned long start = pa_start;
+	unsigned long end = pa_end;

Note that the outercache functions have been doing this cast before this
patch. So now, the cast is just moved into the outercache hook functions.

No functional change.

Signed-off-by: default avatarZhen Lei <thunder.leizhen@huawei.com>
Reviewed-by: default avatarHanjun Guo <guohanjun@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
Signed-off-by: default avatarYuntao Liu <liuyuntao12@huawei.com>
parent 6d225089

arch/arm/include/asm/outercache.h

+3 −3
Original line number Diff line number Diff line
@@ -14,9 +14,9 @@ 
struct l2x0_regs;



struct outer_cache_fns {

	void (*inv_range)(unsigned long, unsigned long);

	void (*clean_range)(unsigned long, unsigned long);

	void (*flush_range)(unsigned long, unsigned long);

	void (*inv_range)(phys_addr_t, phys_addr_t);

	void (*clean_range)(phys_addr_t, phys_addr_t);

	void (*flush_range)(phys_addr_t, phys_addr_t);

	void (*flush_all)(void);

	void (*disable)(void);

#ifdef CONFIG_OUTER_CACHE_SYNC

arch/arm/mm/cache-feroceon-l2.c

+12 −3
Original line number Diff line number Diff line
@@ -165,8 +165,11 @@ static unsigned long calc_range_end(unsigned long start, unsigned long end) 
	return range_end;

}



static void feroceon_l2_inv_range(unsigned long start, unsigned long end)

static void feroceon_l2_inv_range(phys_addr_t pa_start, phys_addr_t pa_end)

{

	unsigned long start = pa_start;

	unsigned long end = pa_end;



	/*

	 * Clean and invalidate partial first cache line.

	 */
@@ -195,8 +198,11 @@ static void feroceon_l2_inv_range(unsigned long start, unsigned long end) 
	dsb();

}



static void feroceon_l2_clean_range(unsigned long start, unsigned long end)

static void feroceon_l2_clean_range(phys_addr_t pa_start, phys_addr_t pa_end)

{

	unsigned long start = pa_start;

	unsigned long end = pa_end;



	/*

	 * If L2 is forced to WT, the L2 will always be clean and we

	 * don't need to do anything here.
@@ -214,8 +220,11 @@ static void feroceon_l2_clean_range(unsigned long start, unsigned long end) 
	dsb();

}



static void feroceon_l2_flush_range(unsigned long start, unsigned long end)

static void feroceon_l2_flush_range(phys_addr_t pa_start, phys_addr_t pa_end)

{

	unsigned long start = pa_start;

	unsigned long end = pa_end;



	start &= ~(CACHE_LINE_SIZE - 1);

	end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);

	while (start != end) {

arch/arm/mm/cache-l2x0.c

+36 −14
Original line number Diff line number Diff line
@@ -184,8 +184,10 @@ static void __l2c210_op_pa_range(void __iomem *reg, unsigned long start, 
	}

}



static void l2c210_inv_range(unsigned long start, unsigned long end)

static void l2c210_inv_range(phys_addr_t pa_start, phys_addr_t pa_end)

{

	unsigned long start = pa_start;

	unsigned long end = pa_end;

	void __iomem *base = l2x0_base;



	if (start & (CACHE_LINE_SIZE - 1)) {
@@ -203,8 +205,10 @@ static void l2c210_inv_range(unsigned long start, unsigned long end) 
	__l2c210_cache_sync(base);

}



static void l2c210_clean_range(unsigned long start, unsigned long end)

static void l2c210_clean_range(phys_addr_t pa_start, phys_addr_t pa_end)

{

	unsigned long start = pa_start;

	unsigned long end = pa_end;

	void __iomem *base = l2x0_base;



	start &= ~(CACHE_LINE_SIZE - 1);
@@ -212,8 +216,10 @@ static void l2c210_clean_range(unsigned long start, unsigned long end) 
	__l2c210_cache_sync(base);

}



static void l2c210_flush_range(unsigned long start, unsigned long end)

static void l2c210_flush_range(phys_addr_t pa_start, phys_addr_t pa_end)

{

	unsigned long start = pa_start;

	unsigned long end = pa_end;

	void __iomem *base = l2x0_base;



	start &= ~(CACHE_LINE_SIZE - 1);
@@ -304,8 +310,10 @@ static unsigned long l2c220_op_pa_range(void __iomem *reg, unsigned long start, 
	return flags;

}



static void l2c220_inv_range(unsigned long start, unsigned long end)

static void l2c220_inv_range(phys_addr_t pa_start, phys_addr_t pa_end)

{

	unsigned long start = pa_start;

	unsigned long end = pa_end;

	void __iomem *base = l2x0_base;

	unsigned long flags;
@@ -331,8 +339,10 @@ static void l2c220_inv_range(unsigned long start, unsigned long end) 
	raw_spin_unlock_irqrestore(&l2x0_lock, flags);

}



static void l2c220_clean_range(unsigned long start, unsigned long end)

static void l2c220_clean_range(phys_addr_t pa_start, phys_addr_t pa_end)

{

	unsigned long start = pa_start;

	unsigned long end = pa_end;

	void __iomem *base = l2x0_base;

	unsigned long flags;
@@ -350,8 +360,10 @@ static void l2c220_clean_range(unsigned long start, unsigned long end) 
	raw_spin_unlock_irqrestore(&l2x0_lock, flags);

}



static void l2c220_flush_range(unsigned long start, unsigned long end)

static void l2c220_flush_range(phys_addr_t pa_start, phys_addr_t pa_end)

{

	unsigned long start = pa_start;

	unsigned long end = pa_end;

	void __iomem *base = l2x0_base;

	unsigned long flags;
@@ -464,8 +476,10 @@ static const struct l2c_init_data l2c220_data = { 
 *	Affects: store buffer

 *	store buffer is not automatically drained.

 */

static void l2c310_inv_range_erratum(unsigned long start, unsigned long end)

static void l2c310_inv_range_erratum(phys_addr_t pa_start, phys_addr_t pa_end)

{

	unsigned long start = pa_start;

	unsigned long end = pa_end;

	void __iomem *base = l2x0_base;



	if ((start | end) & (CACHE_LINE_SIZE - 1)) {
@@ -496,8 +510,10 @@ static void l2c310_inv_range_erratum(unsigned long start, unsigned long end) 
	__l2c210_cache_sync(base);

}



static void l2c310_flush_range_erratum(unsigned long start, unsigned long end)

static void l2c310_flush_range_erratum(phys_addr_t pa_start, phys_addr_t pa_end)

{

	unsigned long start = pa_start;

	unsigned long end = pa_end;

	raw_spinlock_t *lock = &l2x0_lock;

	unsigned long flags;

	void __iomem *base = l2x0_base;
@@ -1400,12 +1416,12 @@ static void aurora_pa_range(unsigned long start, unsigned long end, 
		start = range_end;

	}

}

static void aurora_inv_range(unsigned long start, unsigned long end)

static void aurora_inv_range(phys_addr_t start, phys_addr_t end)

{

	aurora_pa_range(start, end, AURORA_INVAL_RANGE_REG);

}



static void aurora_clean_range(unsigned long start, unsigned long end)

static void aurora_clean_range(phys_addr_t start, phys_addr_t end)

{

	/*

	 * If L2 is forced to WT, the L2 will always be clean and we
@@ -1415,7 +1431,7 @@ static void aurora_clean_range(unsigned long start, unsigned long end) 
		aurora_pa_range(start, end, AURORA_CLEAN_RANGE_REG);

}



static void aurora_flush_range(unsigned long start, unsigned long end)

static void aurora_flush_range(phys_addr_t start, phys_addr_t end)

{

	if (l2_wt_override)

		aurora_pa_range(start, end, AURORA_INVAL_RANGE_REG);
@@ -1604,8 +1620,10 @@ static inline unsigned long bcm_l2_phys_addr(unsigned long addr) 
		return addr + BCM_VC_EMI_OFFSET;

}



static void bcm_inv_range(unsigned long start, unsigned long end)

static void bcm_inv_range(phys_addr_t pa_start, phys_addr_t pa_end)

{

	unsigned long start = pa_start;

	unsigned long end = pa_end;

	unsigned long new_start, new_end;



	BUG_ON(start < BCM_SYS_EMI_START_ADDR);
@@ -1631,8 +1649,10 @@ static void bcm_inv_range(unsigned long start, unsigned long end) 
		new_end);

}



static void bcm_clean_range(unsigned long start, unsigned long end)

static void bcm_clean_range(phys_addr_t pa_start, phys_addr_t pa_end)

{

	unsigned long start = pa_start;

	unsigned long end = pa_end;

	unsigned long new_start, new_end;



	BUG_ON(start < BCM_SYS_EMI_START_ADDR);
@@ -1658,8 +1678,10 @@ static void bcm_clean_range(unsigned long start, unsigned long end) 
		new_end);

}



static void bcm_flush_range(unsigned long start, unsigned long end)

static void bcm_flush_range(phys_addr_t pa_start, phys_addr_t pa_end)

{

	unsigned long start = pa_start;

	unsigned long end = pa_end;

	unsigned long new_start, new_end;



	BUG_ON(start < BCM_SYS_EMI_START_ADDR);

arch/arm/mm/cache-tauros2.c

+12 −3
Original line number Diff line number Diff line
@@ -63,8 +63,11 @@ static inline void tauros2_inv_pa(unsigned long addr) 
 */

#define CACHE_LINE_SIZE		32



static void tauros2_inv_range(unsigned long start, unsigned long end)

static void tauros2_inv_range(phys_addr_t pa_start, phys_addr_t pa_end)

{

	unsigned long start = pa_start;

	unsigned long end = pa_end;



	/*

	 * Clean and invalidate partial first cache line.

	 */
@@ -92,8 +95,11 @@ static void tauros2_inv_range(unsigned long start, unsigned long end) 
	dsb();

}



static void tauros2_clean_range(unsigned long start, unsigned long end)

static void tauros2_clean_range(phys_addr_t pa_start, phys_addr_t pa_end)

{

	unsigned long start = pa_start;

	unsigned long end = pa_end;



	start &= ~(CACHE_LINE_SIZE - 1);

	while (start < end) {

		tauros2_clean_pa(start);
@@ -103,8 +109,11 @@ static void tauros2_clean_range(unsigned long start, unsigned long end) 
	dsb();

}



static void tauros2_flush_range(unsigned long start, unsigned long end)

static void tauros2_flush_range(phys_addr_t pa_start, phys_addr_t pa_end)

{

	unsigned long start = pa_start;

	unsigned long end = pa_end;



	start &= ~(CACHE_LINE_SIZE - 1);

	while (start < end) {

		tauros2_clean_inv_pa(start);

arch/arm/mm/cache-uniphier.c

+3 −3
Original line number Diff line number Diff line
@@ -252,17 +252,17 @@ static void uniphier_cache_maint_all(u32 operation) 
		__uniphier_cache_maint_all(data, operation);

}



static void uniphier_cache_inv_range(unsigned long start, unsigned long end)

static void uniphier_cache_inv_range(phys_addr_t start, phys_addr_t end)

{

	uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_CM_INV);

}



static void uniphier_cache_clean_range(unsigned long start, unsigned long end)

static void uniphier_cache_clean_range(phys_addr_t start, phys_addr_t end)

{

	uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_CM_CLEAN);

}



static void uniphier_cache_flush_range(unsigned long start, unsigned long end)

static void uniphier_cache_flush_range(phys_addr_t start, phys_addr_t end)

{

	uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_CM_FLUSH);

}