Commit bd79d9aa authored by Marek Behún's avatar Marek Behún Committed by David S. Miller
Browse files

net: phy: marvell10g: rename register 



The MV_V2_PORT_MAC_TYPE_* is part of the CTRL register. Rename to
MV_V2_PORT_CTRL_MACTYPE_*.

Signed-off-by: default avatarMarek Behún <kabel@kernel.org>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 3cd52c1e

drivers/net/phy/marvell10g.c

+4 −4
Original line number Diff line number Diff line
@@ -80,8 +80,8 @@ enum { 
	MV_V2_PORT_CTRL		= 0xf001,

	MV_V2_PORT_CTRL_SWRST	= BIT(15),

	MV_V2_PORT_CTRL_PWRDOWN = BIT(11),

	MV_V2_PORT_MAC_TYPE_MASK = 0x7,

	MV_V2_PORT_MAC_TYPE_RATE_MATCH = 0x6,

	MV_V2_PORT_CTRL_MACTYPE_MASK = 0x7,

	MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH = 0x6,

	/* Temperature control/read registers (88X3310 only) */

	MV_V2_TEMP_CTRL		= 0xf08a,

	MV_V2_TEMP_CTRL_MASK	= 0xc000,
@@ -477,8 +477,8 @@ static int mv3310_config_init(struct phy_device *phydev) 
	val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);

	if (val < 0)

		return val;

	priv->rate_match = ((val & MV_V2_PORT_MAC_TYPE_MASK) ==

			MV_V2_PORT_MAC_TYPE_RATE_MATCH);

	priv->rate_match = ((val & MV_V2_PORT_CTRL_MACTYPE_MASK) ==

			MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH);



	/* Enable EDPD mode - saving 600mW */

	return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);