Commit bd4bb225 authored by Taniya Das's avatar Taniya Das Committed by Stephen Boyd
Browse files

clk: qcom: gcc: Add support for Secure control source clock 



The secure controller driver requires to request for various frequencies
on the source clock, thus add support for the same.

Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/1589709861-27580-4-git-send-email-tdas@codeaurora.org


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 3005b17c

drivers/clk/qcom/gcc-sc7180.c

+21 −0
Original line number Diff line number Diff line
@@ -817,6 +817,26 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 
	},

};



static const struct freq_tbl ftbl_gcc_sec_ctrl_clk_src[] = {

	F(4800000, P_BI_TCXO, 4, 0, 0),

	F(19200000, P_BI_TCXO, 1, 0, 0),

	{ }

};



static struct clk_rcg2 gcc_sec_ctrl_clk_src = {

	.cmd_rcgr = 0x3d030,

	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = gcc_parent_map_3,

	.freq_tbl = ftbl_gcc_sec_ctrl_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_sec_ctrl_clk_src",

		.parent_data = gcc_parent_data_3,

		.num_parents = ARRAY_SIZE(gcc_parent_data_3),

		.ops = &clk_rcg2_ops,

	},

};



static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {

	.halt_reg = 0x82024,

	.halt_check = BRANCH_HALT_DELAY,
@@ -2407,6 +2427,7 @@ static struct clk_regmap *gcc_sc7180_clocks[] = { 
	[GCC_MSS_NAV_AXI_CLK] = &gcc_mss_nav_axi_clk.clkr,

	[GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,

	[GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,

	[GCC_SEC_CTRL_CLK_SRC] = &gcc_sec_ctrl_clk_src.clkr,

};



static const struct qcom_reset_map gcc_sc7180_resets[] = {