Commit bd3c9cdb authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 fixes from Catalin Marinas:
 "Fixes and cpucaps.h automatic generation:

   - Generate cpucaps.h at build time rather than carrying lots of
     #defines. Merged at -rc1 to avoid some conflicts during the merge
     window.

   - Initialise RGSR_EL1.SEED in __cpu_setup() as it may be left as 0
     out of reset and the IRG instruction would not function as expected
     if only the architected pseudorandom number generator is
     implemented.

   - Fix potential race condition in __sync_icache_dcache() where the
     PG_dcache_clean page flag is set before the actual cache
     maintenance.

   - Fix header include in BTI kselftests"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: Fix race condition on PG_dcache_clean in __sync_icache_dcache()
  arm64: tools: Add __ASM_CPUCAPS_H to the endif in cpucaps.h
  arm64: mte: initialize RGSR_EL1.SEED in __cpu_setup
  kselftest/arm64: Add missing stddef.h include to BTI tests
  arm64: Generate cpucaps.h
parents ac524ece 588a513d

arch/arm64/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -175,6 +175,9 @@ vdso_install: 
	$(if $(CONFIG_COMPAT_VDSO), \

		$(Q)$(MAKE) $(build)=arch/arm64/kernel/vdso32 $@)



archprepare:

	$(Q)$(MAKE) $(build)=arch/arm64/tools kapi



# We use MRPROPER_FILES and CLEAN_FILES now

archclean:

	$(Q)$(MAKE) $(clean)=$(boot)

arch/arm64/include/asm/Kbuild

+2 −0
Original line number Diff line number Diff line
@@ -5,3 +5,5 @@ generic-y += qrwlock.h 
generic-y += qspinlock.h

generic-y += set_memory.h

generic-y += user.h



generated-y += cpucaps.h

arch/arm64/include/asm/cpucaps.h

deleted100644 → 0
+0 −74
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * arch/arm64/include/asm/cpucaps.h

 *

 * Copyright (C) 2016 ARM Ltd.

 */

#ifndef __ASM_CPUCAPS_H

#define __ASM_CPUCAPS_H



#define ARM64_WORKAROUND_CLEAN_CACHE		0

#define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE	1

#define ARM64_WORKAROUND_845719			2

#define ARM64_HAS_SYSREG_GIC_CPUIF		3

#define ARM64_HAS_PAN				4

#define ARM64_HAS_LSE_ATOMICS			5

#define ARM64_WORKAROUND_CAVIUM_23154		6

#define ARM64_WORKAROUND_834220			7

#define ARM64_HAS_NO_HW_PREFETCH		8

#define ARM64_HAS_VIRT_HOST_EXTN		11

#define ARM64_WORKAROUND_CAVIUM_27456		12

#define ARM64_HAS_32BIT_EL0			13

#define ARM64_SPECTRE_V3A			14

#define ARM64_HAS_CNP				15

#define ARM64_HAS_NO_FPSIMD			16

#define ARM64_WORKAROUND_REPEAT_TLBI		17

#define ARM64_WORKAROUND_QCOM_FALKOR_E1003	18

#define ARM64_WORKAROUND_858921			19

#define ARM64_WORKAROUND_CAVIUM_30115		20

#define ARM64_HAS_DCPOP				21

#define ARM64_SVE				22

#define ARM64_UNMAP_KERNEL_AT_EL0		23

#define ARM64_SPECTRE_V2			24

#define ARM64_HAS_RAS_EXTN			25

#define ARM64_WORKAROUND_843419			26

#define ARM64_HAS_CACHE_IDC			27

#define ARM64_HAS_CACHE_DIC			28

#define ARM64_HW_DBM				29

#define ARM64_SPECTRE_V4			30

#define ARM64_MISMATCHED_CACHE_TYPE		31

#define ARM64_HAS_STAGE2_FWB			32

#define ARM64_HAS_CRC32				33

#define ARM64_SSBS				34

#define ARM64_WORKAROUND_1418040		35

#define ARM64_HAS_SB				36

#define ARM64_WORKAROUND_SPECULATIVE_AT		37

#define ARM64_HAS_ADDRESS_AUTH_ARCH		38

#define ARM64_HAS_ADDRESS_AUTH_IMP_DEF		39

#define ARM64_HAS_GENERIC_AUTH_ARCH		40

#define ARM64_HAS_GENERIC_AUTH_IMP_DEF		41

#define ARM64_HAS_IRQ_PRIO_MASKING		42

#define ARM64_HAS_DCPODP			43

#define ARM64_WORKAROUND_1463225		44

#define ARM64_WORKAROUND_CAVIUM_TX2_219_TVM	45

#define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM	46

#define ARM64_WORKAROUND_1542419		47

#define ARM64_HAS_E0PD				48

#define ARM64_HAS_RNG				49

#define ARM64_HAS_AMU_EXTN			50

#define ARM64_HAS_ADDRESS_AUTH			51

#define ARM64_HAS_GENERIC_AUTH			52

#define ARM64_HAS_32BIT_EL1			53

#define ARM64_BTI				54

#define ARM64_HAS_ARMv8_4_TTL			55

#define ARM64_HAS_TLB_RANGE			56

#define ARM64_MTE				57

#define ARM64_WORKAROUND_1508412		58

#define ARM64_HAS_LDAPR				59

#define ARM64_KVM_PROTECTED_MODE		60

#define ARM64_WORKAROUND_NVIDIA_CARMEL_CNP	61

#define ARM64_HAS_EPAN				62



#define ARM64_NCAPS				63



#endif /* __ASM_CPUCAPS_H */

arch/arm64/mm/flush.c

+3 −1
Original line number Diff line number Diff line
@@ -55,8 +55,10 @@ void __sync_icache_dcache(pte_t pte) 
{

	struct page *page = pte_page(pte);



	if (!test_and_set_bit(PG_dcache_clean, &page->flags))

	if (!test_bit(PG_dcache_clean, &page->flags)) {

		sync_icache_aliases(page_address(page), page_size(page));

		set_bit(PG_dcache_clean, &page->flags);

	}

}

EXPORT_SYMBOL_GPL(__sync_icache_dcache);

arch/arm64/mm/proc.S

+12 −0
Original line number Diff line number Diff line
@@ -447,6 +447,18 @@ SYM_FUNC_START(__cpu_setup) 
	mov	x10, #(SYS_GCR_EL1_RRND | SYS_GCR_EL1_EXCL_MASK)

	msr_s	SYS_GCR_EL1, x10



	/*

	 * If GCR_EL1.RRND=1 is implemented the same way as RRND=0, then

	 * RGSR_EL1.SEED must be non-zero for IRG to produce

	 * pseudorandom numbers. As RGSR_EL1 is UNKNOWN out of reset, we

	 * must initialize it.

	 */

	mrs	x10, CNTVCT_EL0

	ands	x10, x10, #SYS_RGSR_EL1_SEED_MASK

	csinc	x10, x10, xzr, ne

	lsl	x10, x10, #SYS_RGSR_EL1_SEED_SHIFT

	msr_s	SYS_RGSR_EL1, x10



	/* clear any pending tag check faults in TFSR*_EL1 */

	msr_s	SYS_TFSR_EL1, xzr

	msr_s	SYS_TFSRE0_EL1, xzr