dt-bindings: clock: Add StarFive JH7110 PLL clock generator

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: StarFive JH7110 PLL Clock Generator

description:

  These PLLs are high speed, low jitter frequency synthesizers in the JH7110.

  Each PLL works in integer mode or fraction mode, with configuration

  registers in the sys syscon. So the PLLs node should be a child of

  SYS-SYSCON node.

  The formula for calculating frequency is

  Fvco = Fref * (NI + NF) / M / Q1

maintainers:

  - Xingyu Wu <xingyu.wu@starfivetech.com>

properties:

  compatible:

    const: starfive,jh7110-pll

  clocks:

    maxItems: 1

    description: Main Oscillator (24 MHz)

  '#clock-cells':

    const: 1

    description:

      See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.

required:

  - compatible

  - clocks

  - '#clock-cells'

additionalProperties: false

examples:

  - |

    clock-controller {

      compatible = "starfive,jh7110-pll";

      clocks = <&osc>;

      #clock-cells = <1>;

    };

#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__

#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__

/* PLL clocks */

#define JH7110_PLLCLK_PLL0_OUT			0

#define JH7110_PLLCLK_PLL1_OUT			1

#define JH7110_PLLCLK_PLL2_OUT			2

#define JH7110_PLLCLK_END			3

/* SYSCRG clocks */

#define JH7110_SYSCLK_CPU_ROOT			0

#define JH7110_SYSCLK_CPU_CORE			1