Commit bd1de1a0 authored by Ravi Bangoria's avatar Ravi Bangoria Committed by Paul Mackerras
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KVM: PPC: Book3S HV: Add infrastructure to support 2nd DAWR



KVM code assumes single DAWR everywhere. Add code to support 2nd DAWR.
DAWR is a hypervisor resource and thus H_SET_MODE hcall is used to set/
unset it. Introduce new case H_SET_MODE_RESOURCE_SET_DAWR1 for 2nd DAWR.
Also, KVM will support 2nd DAWR only if CPU_FTR_DAWR1 is set.

Signed-off-by: default avatarRavi Bangoria <ravi.bangoria@linux.ibm.com>
Signed-off-by: default avatarPaul Mackerras <paulus@ozlabs.org>
parent 122954ed
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+2 −0
Original line number Diff line number Diff line
@@ -2276,6 +2276,8 @@ registers, find a list below:
  PPC     KVM_REG_PPC_PSSCR               64
  PPC     KVM_REG_PPC_DEC_EXPIRY          64
  PPC     KVM_REG_PPC_PTCR                64
  PPC     KVM_REG_PPC_DAWR1               64
  PPC     KVM_REG_PPC_DAWRX1              64
  PPC     KVM_REG_PPC_TM_GPR0             64
  ...
  PPC     KVM_REG_PPC_TM_GPR31            64
+7 −1
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@@ -569,16 +569,22 @@ struct hv_guest_state {
	u64 pidr;
	u64 cfar;
	u64 ppr;
	/* Version 1 ends here */
	u64 dawr1;
	u64 dawrx1;
	/* Version 2 ends here */
};

/* Latest version of hv_guest_state structure */
#define HV_GUEST_STATE_VERSION	1
#define HV_GUEST_STATE_VERSION	2

static inline int hv_guest_state_size(unsigned int version)
{
	switch (version) {
	case 1:
		return offsetofend(struct hv_guest_state, ppr);
	case 2:
		return offsetofend(struct hv_guest_state, dawrx1);
	default:
		return -1;
	}
+3 −0
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@@ -306,6 +306,7 @@ struct kvm_arch {
	u8 svm_enabled;
	bool threads_indep;
	bool nested_enable;
	bool dawr1_enabled;
	pgd_t *pgtable;
	u64 process_table;
	struct dentry *debugfs_dir;
@@ -585,6 +586,8 @@ struct kvm_vcpu_arch {
	ulong dabr;
	ulong dawr0;
	ulong dawrx0;
	ulong dawr1;
	ulong dawrx1;
	ulong ciabr;
	ulong cfar;
	ulong ppr;
+2 −0
Original line number Diff line number Diff line
@@ -644,6 +644,8 @@ struct kvm_ppc_cpu_char {
#define KVM_REG_PPC_MMCR3	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc1)
#define KVM_REG_PPC_SIER2	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc2)
#define KVM_REG_PPC_SIER3	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc3)
#define KVM_REG_PPC_DAWR1	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc4)
#define KVM_REG_PPC_DAWRX1	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc5)

/* Transactional Memory checkpointed state:
 * This is all GPRs, all VSX regs and a subset of SPRs
+2 −0
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@@ -528,6 +528,8 @@ int main(void)
	OFFSET(VCPU_DABRX, kvm_vcpu, arch.dabrx);
	OFFSET(VCPU_DAWR0, kvm_vcpu, arch.dawr0);
	OFFSET(VCPU_DAWRX0, kvm_vcpu, arch.dawrx0);
	OFFSET(VCPU_DAWR1, kvm_vcpu, arch.dawr1);
	OFFSET(VCPU_DAWRX1, kvm_vcpu, arch.dawrx1);
	OFFSET(VCPU_CIABR, kvm_vcpu, arch.ciabr);
	OFFSET(VCPU_HFLAGS, kvm_vcpu, arch.hflags);
	OFFSET(VCPU_DEC, kvm_vcpu, arch.dec);
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