Commit bd194611 authored by Ingo Molnar's avatar Ingo Molnar
Browse files

Merge branch 'x86/urgent' into x86/core, to resolve conflict 



There's a conflict between the call-depth tracking commits in x86/core:

  ee3e2469 ("x86/ftrace: Make it call depth tracking aware")
  36b64f10 ("x86/ftrace: Rebalance RSB")
  eac828ea ("x86/ftrace: Remove ftrace_epilogue()")

And these fixes in x86/urgent:

  883bbbff ("ftrace,kcfi: Separate ftrace_stub() and ftrace_stub_graph()")
  b5f1fc31 ("x86/ftrace: Remove ftrace_epilogue()")

It's non-trivial overlapping modifications - resolve them.

 Conflicts:
	arch/x86/kernel/ftrace_64.S

Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parents dbf53a29 471f0aa7

arch/arm64/kernel/entry-ftrace.S

+6 −1
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
 */



#include <linux/linkage.h>

#include <linux/cfi_types.h>

#include <asm/asm-offsets.h>

#include <asm/assembler.h>

#include <asm/ftrace.h>
@@ -294,10 +295,14 @@ SYM_FUNC_END(ftrace_graph_caller) 
#endif /* CONFIG_FUNCTION_GRAPH_TRACER */

#endif /* CONFIG_DYNAMIC_FTRACE_WITH_REGS */



SYM_FUNC_START(ftrace_stub)

SYM_TYPED_FUNC_START(ftrace_stub)

	ret

SYM_FUNC_END(ftrace_stub)



SYM_TYPED_FUNC_START(ftrace_stub_graph)

	ret

SYM_FUNC_END(ftrace_stub_graph)



#ifdef CONFIG_FUNCTION_GRAPH_TRACER

/*

 * void return_to_handler(void)

arch/x86/Kconfig

+0 −1
Original line number Diff line number Diff line
@@ -1975,7 +1975,6 @@ config EFI 
config EFI_STUB

	bool "EFI stub support"

	depends on EFI

	depends on $(cc-option,-mabi=ms) || X86_32

	select RELOCATABLE

	help

	  This kernel feature allows a bzImage to be loaded directly

arch/x86/events/intel/lbr.c

+1 −1
Original line number Diff line number Diff line
@@ -1596,7 +1596,7 @@ void __init intel_pmu_arch_lbr_init(void) 
	return;



clear_arch_lbr:

	clear_cpu_cap(&boot_cpu_data, X86_FEATURE_ARCH_LBR);

	setup_clear_cpu_cap(X86_FEATURE_ARCH_LBR);

}



/**

arch/x86/kernel/cpu/microcode/amd.c

+13 −3
Original line number Diff line number Diff line
@@ -440,7 +440,13 @@ apply_microcode_early_amd(u32 cpuid_1_eax, void *ucode, size_t size, bool save_p 
		return ret;



	native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);

	if (rev >= mc->hdr.patch_id)



	/*

	 * Allow application of the same revision to pick up SMT-specific

	 * changes even if the revision of the other SMT thread is already

	 * up-to-date.

	 */

	if (rev > mc->hdr.patch_id)

		return ret;



	if (!__apply_microcode_amd(mc)) {
@@ -528,8 +534,12 @@ void load_ucode_amd_ap(unsigned int cpuid_1_eax) 


	native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);



	/* Check whether we have saved a new patch already: */

	if (*new_rev && rev < mc->hdr.patch_id) {

	/*

	 * Check whether a new patch has been saved already. Also, allow application of

	 * the same revision in order to pick up SMT-thread-specific configuration even

	 * if the sibling SMT thread already has an up-to-date revision.

	 */

	if (*new_rev && rev <= mc->hdr.patch_id) {

		if (!__apply_microcode_amd(mc)) {

			*new_rev = mc->hdr.patch_id;

			return;

arch/x86/kernel/cpu/resctrl/core.c

+2 −6
Original line number Diff line number Diff line
@@ -66,9 +66,6 @@ struct rdt_hw_resource rdt_resources_all[] = { 
			.rid			= RDT_RESOURCE_L3,

			.name			= "L3",

			.cache_level		= 3,

			.cache = {

				.min_cbm_bits	= 1,

			},

			.domains		= domain_init(RDT_RESOURCE_L3),

			.parse_ctrlval		= parse_cbm,

			.format_str		= "%d=%0*x",
@@ -83,9 +80,6 @@ struct rdt_hw_resource rdt_resources_all[] = { 
			.rid			= RDT_RESOURCE_L2,

			.name			= "L2",

			.cache_level		= 2,

			.cache = {

				.min_cbm_bits	= 1,

			},

			.domains		= domain_init(RDT_RESOURCE_L2),

			.parse_ctrlval		= parse_cbm,

			.format_str		= "%d=%0*x",
@@ -836,6 +830,7 @@ static __init void rdt_init_res_defs_intel(void) 
			r->cache.arch_has_sparse_bitmaps = false;

			r->cache.arch_has_empty_bitmaps = false;

			r->cache.arch_has_per_cpu_cfg = false;

			r->cache.min_cbm_bits = 1;

		} else if (r->rid == RDT_RESOURCE_MBA) {

			hw_res->msr_base = MSR_IA32_MBA_THRTL_BASE;

			hw_res->msr_update = mba_wrmsr_intel;
@@ -856,6 +851,7 @@ static __init void rdt_init_res_defs_amd(void) 
			r->cache.arch_has_sparse_bitmaps = true;

			r->cache.arch_has_empty_bitmaps = true;

			r->cache.arch_has_per_cpu_cfg = true;

			r->cache.min_cbm_bits = 0;

		} else if (r->rid == RDT_RESOURCE_MBA) {

			hw_res->msr_base = MSR_IA32_MBA_BW_BASE;

			hw_res->msr_update = mba_wrmsr_amd;