Loading Documentation/ABI/testing/debugfs-driver-habanalabs +10 −1 Original line number Diff line number Diff line Loading @@ -16,7 +16,16 @@ Description: Allow the root user to disable/enable in runtime the clock gating mechanism in Gaudi. Due to how Gaudi is built, the clock gating needs to be disabled in order to access the registers of the TPC and MME engines. This is sometimes needed during debug by the user and hence the user needs this option during debug by the user and hence the user needs this option. The user can supply a bitmask value, each bit represents a different engine to disable/enable its clock gating feature. The bitmask is composed of 20 bits: 0 - 7 : DMA channels 8 - 11 : MME engines 12 - 19 : TPC engines The bit's location of a specific engine can be determined using (1 << GAUDI_ENGINE_ID_*). GAUDI_ENGINE_ID_* values are defined in uapi habanalabs.h file in enum gaudi_engine_id What: /sys/kernel/debug/habanalabs/hl<n>/command_buffers Date: Jan 2019 Loading Documentation/devicetree/bindings/media/allwinner,sun4i-a10-video-engine.yaml +3 −0 Original line number Diff line number Diff line Loading @@ -47,6 +47,9 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle-array description: Phandle to the device SRAM iommus: maxItems: 1 memory-region: description: CMA pool to use for buffers allocation instead of the default Loading Documentation/networking/bareudp.rst +2 −3 Original line number Diff line number Diff line Loading @@ -8,9 +8,8 @@ There are various L3 encapsulation standards using UDP being discussed to leverage the UDP based load balancing capability of different networks. MPLSoUDP (__ https://tools.ietf.org/html/rfc7510) is one among them. The Bareudp tunnel module provides a generic L3 encapsulation tunnelling support for tunnelling different L3 protocols like MPLS, IP, NSH etc. inside a UDP tunnel. The Bareudp tunnel module provides a generic L3 encapsulation support for tunnelling different L3 protocols like MPLS, IP, NSH etc. inside a UDP tunnel. Special Handling ---------------- Loading Documentation/networking/devlink/devlink-trap.rst +4 −0 Original line number Diff line number Diff line Loading @@ -486,6 +486,10 @@ narrow. The description of these groups must be added to the following table: - Contains packet traps for packets that should be locally delivered after routing, but do not match more specific packet traps (e.g., ``ipv4_bgp``) * - ``external_delivery`` - Contains packet traps for packets that should be routed through an external interface (e.g., management interface) that does not belong to the same device (e.g., switch ASIC) as the ingress interface * - ``ipv6`` - Contains packet traps for various IPv6 control packets (e.g., Router Advertisements) Loading MAINTAINERS +4 −3 Original line number Diff line number Diff line Loading @@ -782,7 +782,7 @@ F: include/dt-bindings/reset/altr,rst-mgr-a10sr.h F: include/linux/mfd/altera-a10sr.h ALTERA TRIPLE SPEED ETHERNET DRIVER M: Thor Thayer <thor.thayer@linux.intel.com> M: Joyce Ooi <joyce.ooi@intel.com> L: netdev@vger.kernel.org S: Maintained F: drivers/net/ethernet/altera/ Loading Loading @@ -1425,7 +1425,7 @@ F: arch/arm*/include/asm/perf_event.h F: arch/arm*/kernel/hw_breakpoint.c F: arch/arm*/kernel/perf_* F: arch/arm/oprofile/common.c F: drivers/perf/* F: drivers/perf/ F: include/linux/perf/arm_pmu.h ARM PORT Loading Loading @@ -14191,7 +14191,8 @@ F: Documentation/devicetree/bindings/net/qcom,ethqos.txt F: drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c QUALCOMM GENERIC INTERFACE I2C DRIVER M: Alok Chauhan <alokc@codeaurora.org> M: Akash Asthana <akashast@codeaurora.org> M: Mukesh Savaliya <msavaliy@codeaurora.org> L: linux-i2c@vger.kernel.org L: linux-arm-msm@vger.kernel.org S: Supported Loading Loading
Documentation/ABI/testing/debugfs-driver-habanalabs +10 −1 Original line number Diff line number Diff line Loading @@ -16,7 +16,16 @@ Description: Allow the root user to disable/enable in runtime the clock gating mechanism in Gaudi. Due to how Gaudi is built, the clock gating needs to be disabled in order to access the registers of the TPC and MME engines. This is sometimes needed during debug by the user and hence the user needs this option during debug by the user and hence the user needs this option. The user can supply a bitmask value, each bit represents a different engine to disable/enable its clock gating feature. The bitmask is composed of 20 bits: 0 - 7 : DMA channels 8 - 11 : MME engines 12 - 19 : TPC engines The bit's location of a specific engine can be determined using (1 << GAUDI_ENGINE_ID_*). GAUDI_ENGINE_ID_* values are defined in uapi habanalabs.h file in enum gaudi_engine_id What: /sys/kernel/debug/habanalabs/hl<n>/command_buffers Date: Jan 2019 Loading
Documentation/devicetree/bindings/media/allwinner,sun4i-a10-video-engine.yaml +3 −0 Original line number Diff line number Diff line Loading @@ -47,6 +47,9 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle-array description: Phandle to the device SRAM iommus: maxItems: 1 memory-region: description: CMA pool to use for buffers allocation instead of the default Loading
Documentation/networking/bareudp.rst +2 −3 Original line number Diff line number Diff line Loading @@ -8,9 +8,8 @@ There are various L3 encapsulation standards using UDP being discussed to leverage the UDP based load balancing capability of different networks. MPLSoUDP (__ https://tools.ietf.org/html/rfc7510) is one among them. The Bareudp tunnel module provides a generic L3 encapsulation tunnelling support for tunnelling different L3 protocols like MPLS, IP, NSH etc. inside a UDP tunnel. The Bareudp tunnel module provides a generic L3 encapsulation support for tunnelling different L3 protocols like MPLS, IP, NSH etc. inside a UDP tunnel. Special Handling ---------------- Loading
Documentation/networking/devlink/devlink-trap.rst +4 −0 Original line number Diff line number Diff line Loading @@ -486,6 +486,10 @@ narrow. The description of these groups must be added to the following table: - Contains packet traps for packets that should be locally delivered after routing, but do not match more specific packet traps (e.g., ``ipv4_bgp``) * - ``external_delivery`` - Contains packet traps for packets that should be routed through an external interface (e.g., management interface) that does not belong to the same device (e.g., switch ASIC) as the ingress interface * - ``ipv6`` - Contains packet traps for various IPv6 control packets (e.g., Router Advertisements) Loading
MAINTAINERS +4 −3 Original line number Diff line number Diff line Loading @@ -782,7 +782,7 @@ F: include/dt-bindings/reset/altr,rst-mgr-a10sr.h F: include/linux/mfd/altera-a10sr.h ALTERA TRIPLE SPEED ETHERNET DRIVER M: Thor Thayer <thor.thayer@linux.intel.com> M: Joyce Ooi <joyce.ooi@intel.com> L: netdev@vger.kernel.org S: Maintained F: drivers/net/ethernet/altera/ Loading Loading @@ -1425,7 +1425,7 @@ F: arch/arm*/include/asm/perf_event.h F: arch/arm*/kernel/hw_breakpoint.c F: arch/arm*/kernel/perf_* F: arch/arm/oprofile/common.c F: drivers/perf/* F: drivers/perf/ F: include/linux/perf/arm_pmu.h ARM PORT Loading Loading @@ -14191,7 +14191,8 @@ F: Documentation/devicetree/bindings/net/qcom,ethqos.txt F: drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c QUALCOMM GENERIC INTERFACE I2C DRIVER M: Alok Chauhan <alokc@codeaurora.org> M: Akash Asthana <akashast@codeaurora.org> M: Mukesh Savaliya <msavaliy@codeaurora.org> L: linux-i2c@vger.kernel.org L: linux-arm-msm@vger.kernel.org S: Supported Loading