drm/amd/psp: Add C2P registers to mp_13_0_2 header (bce04f21) · Commits · EulixOS / Software / Kernel

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_offset.h

+48 −0

Original line number	Diff line number	Diff line
		@@ -172,6 +172,54 @@
		#define regMP0_SMN_C2PMSG_102_BASE_IDX 0
		#define regMP0_SMN_C2PMSG_103 0x00a7
		#define regMP0_SMN_C2PMSG_103_BASE_IDX 0
		#define regMP0_SMN_C2PMSG_104 0x00a8
		#define regMP0_SMN_C2PMSG_104_BASE_IDX 0
		#define regMP0_SMN_C2PMSG_105 0x00a9
		#define regMP0_SMN_C2PMSG_105_BASE_IDX 0
		#define regMP0_SMN_C2PMSG_106 0x00aa
		#define regMP0_SMN_C2PMSG_106_BASE_IDX 0
		#define regMP0_SMN_C2PMSG_107 0x00ab
		#define regMP0_SMN_C2PMSG_107_BASE_IDX 0
		#define regMP0_SMN_C2PMSG_108 0x00ac
		#define regMP0_SMN_C2PMSG_108_BASE_IDX 0
		#define regMP0_SMN_C2PMSG_109 0x00ad
		#define regMP0_SMN_C2PMSG_109_BASE_IDX 0
		#define regMP0_SMN_C2PMSG_110 0x00ae
		#define regMP0_SMN_C2PMSG_110_BASE_IDX 0
		#define regMP0_SMN_C2PMSG_111 0x00af
		#define regMP0_SMN_C2PMSG_111_BASE_IDX 0
		#define regMP0_SMN_C2PMSG_112 0x00b0
		#define regMP0_SMN_C2PMSG_112_BASE_IDX 0
		#define regMP0_SMN_C2PMSG_113 0x00b1
		#define regMP0_SMN_C2PMSG_113_BASE_IDX 0
		#define regMP0_SMN_C2PMSG_114 0x00b2
		#define regMP0_SMN_C2PMSG_114_BASE_IDX 0
		#define regMP0_SMN_C2PMSG_115 0x00b3
		#define regMP0_SMN_C2PMSG_115_BASE_IDX 0
		#define regMP0_SMN_C2PMSG_116 0x00b4
		#define regMP0_SMN_C2PMSG_116_BASE_IDX 0
		#define regMP0_SMN_C2PMSG_117 0x00b5
		#define regMP0_SMN_C2PMSG_117_BASE_IDX 0
		#define regMP0_SMN_C2PMSG_118 0x00b6
		#define regMP0_SMN_C2PMSG_118_BASE_IDX 0
		#define regMP0_SMN_C2PMSG_119 0x00b7
		#define regMP0_SMN_C2PMSG_119_BASE_IDX 0
		#define regMP0_SMN_C2PMSG_120 0x00b8
		#define regMP0_SMN_C2PMSG_120_BASE_IDX 0
		#define regMP0_SMN_C2PMSG_121 0x00b9
		#define regMP0_SMN_C2PMSG_121_BASE_IDX 0
		#define regMP0_SMN_C2PMSG_122 0x00ba
		#define regMP0_SMN_C2PMSG_122_BASE_IDX 0
		#define regMP0_SMN_C2PMSG_123 0x00bb
		#define regMP0_SMN_C2PMSG_123_BASE_IDX 0
		#define regMP0_SMN_C2PMSG_124 0x00bc
		#define regMP0_SMN_C2PMSG_124_BASE_IDX 0
		#define regMP0_SMN_C2PMSG_125 0x00bd
		#define regMP0_SMN_C2PMSG_125_BASE_IDX 0
		#define regMP0_SMN_C2PMSG_126 0x00be
		#define regMP0_SMN_C2PMSG_126_BASE_IDX 0
		#define regMP0_SMN_C2PMSG_127 0x00bf
		#define regMP0_SMN_C2PMSG_127_BASE_IDX 0
		#define regMP0_SMN_IH_CREDIT 0x00c1
		#define regMP0_SMN_IH_CREDIT_BASE_IDX 0
		#define regMP0_SMN_IH_SW_INT 0x00c2

drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_sh_mask.h

+72 −0

Original line number	Diff line number	Diff line
		@@ -484,6 +484,78 @@
		//MP1_SMN_C2PMSG_103
		#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
		#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
		//MP1_SMN_C2PMSG_104
		#define MP1_SMN_C2PMSG_104__CONTENT__SHIFT 0x0
		#define MP1_SMN_C2PMSG_104__CONTENT_MASK 0xFFFFFFFFL
		//MP1_SMN_C2PMSG_105
		#define MP1_SMN_C2PMSG_105__CONTENT__SHIFT 0x0
		#define MP1_SMN_C2PMSG_105__CONTENT_MASK 0xFFFFFFFFL
		//MP1_SMN_C2PMSG_106
		#define MP1_SMN_C2PMSG_106__CONTENT__SHIFT 0x0
		#define MP1_SMN_C2PMSG_106__CONTENT_MASK 0xFFFFFFFFL
		//MP1_SMN_C2PMSG_107
		#define MP1_SMN_C2PMSG_107__CONTENT__SHIFT 0x0
		#define MP1_SMN_C2PMSG_107__CONTENT_MASK 0xFFFFFFFFL
		//MP1_SMN_C2PMSG_108
		#define MP1_SMN_C2PMSG_108__CONTENT__SHIFT 0x0
		#define MP1_SMN_C2PMSG_108__CONTENT_MASK 0xFFFFFFFFL
		//MP1_SMN_C2PMSG_109
		#define MP1_SMN_C2PMSG_109__CONTENT__SHIFT 0x0
		#define MP1_SMN_C2PMSG_109__CONTENT_MASK 0xFFFFFFFFL
		//MP1_SMN_C2PMSG_110
		#define MP1_SMN_C2PMSG_110__CONTENT__SHIFT 0x0
		#define MP1_SMN_C2PMSG_110__CONTENT_MASK 0xFFFFFFFFL
		//MP1_SMN_C2PMSG_111
		#define MP1_SMN_C2PMSG_111__CONTENT__SHIFT 0x0
		#define MP1_SMN_C2PMSG_111__CONTENT_MASK 0xFFFFFFFFL
		//MP1_SMN_C2PMSG_112
		#define MP1_SMN_C2PMSG_112__CONTENT__SHIFT 0x0
		#define MP1_SMN_C2PMSG_112__CONTENT_MASK 0xFFFFFFFFL
		//MP1_SMN_C2PMSG_113
		#define MP1_SMN_C2PMSG_113__CONTENT__SHIFT 0x0
		#define MP1_SMN_C2PMSG_113__CONTENT_MASK 0xFFFFFFFFL
		//MP1_SMN_C2PMSG_114
		#define MP1_SMN_C2PMSG_114__CONTENT__SHIFT 0x0
		#define MP1_SMN_C2PMSG_114__CONTENT_MASK 0xFFFFFFFFL
		//MP1_SMN_C2PMSG_115
		#define MP1_SMN_C2PMSG_115__CONTENT__SHIFT 0x0
		#define MP1_SMN_C2PMSG_115__CONTENT_MASK 0xFFFFFFFFL
		//MP1_SMN_C2PMSG_116
		#define MP1_SMN_C2PMSG_116__CONTENT__SHIFT 0x0
		#define MP1_SMN_C2PMSG_116__CONTENT_MASK 0xFFFFFFFFL
		//MP1_SMN_C2PMSG_117
		#define MP1_SMN_C2PMSG_117__CONTENT__SHIFT 0x0
		#define MP1_SMN_C2PMSG_117__CONTENT_MASK 0xFFFFFFFFL
		//MP1_SMN_C2PMSG_118
		#define MP1_SMN_C2PMSG_118__CONTENT__SHIFT 0x0
		#define MP1_SMN_C2PMSG_118__CONTENT_MASK 0xFFFFFFFFL
		//MP1_SMN_C2PMSG_119
		#define MP1_SMN_C2PMSG_119__CONTENT__SHIFT 0x0
		#define MP1_SMN_C2PMSG_119__CONTENT_MASK 0xFFFFFFFFL
		//MP1_SMN_C2PMSG_120
		#define MP1_SMN_C2PMSG_120__CONTENT__SHIFT 0x0
		#define MP1_SMN_C2PMSG_120__CONTENT_MASK 0xFFFFFFFFL
		//MP1_SMN_C2PMSG_121
		#define MP1_SMN_C2PMSG_121__CONTENT__SHIFT 0x0
		#define MP1_SMN_C2PMSG_121__CONTENT_MASK 0xFFFFFFFFL
		//MP1_SMN_C2PMSG_122
		#define MP1_SMN_C2PMSG_122__CONTENT__SHIFT 0x0
		#define MP1_SMN_C2PMSG_122__CONTENT_MASK 0xFFFFFFFFL
		//MP1_SMN_C2PMSG_123
		#define MP1_SMN_C2PMSG_123__CONTENT__SHIFT 0x0
		#define MP1_SMN_C2PMSG_123__CONTENT_MASK 0xFFFFFFFFL
		//MP1_SMN_C2PMSG_124
		#define MP1_SMN_C2PMSG_124__CONTENT__SHIFT 0x0
		#define MP1_SMN_C2PMSG_124__CONTENT_MASK 0xFFFFFFFFL
		//MP1_SMN_C2PMSG_125
		#define MP1_SMN_C2PMSG_125__CONTENT__SHIFT 0x0
		#define MP1_SMN_C2PMSG_125__CONTENT_MASK 0xFFFFFFFFL
		//MP1_SMN_C2PMSG_126
		#define MP1_SMN_C2PMSG_126__CONTENT__SHIFT 0x0
		#define MP1_SMN_C2PMSG_126__CONTENT_MASK 0xFFFFFFFFL
		//MP1_SMN_C2PMSG_127
		#define MP1_SMN_C2PMSG_127__CONTENT__SHIFT 0x0
		#define MP1_SMN_C2PMSG_127__CONTENT_MASK 0xFFFFFFFFL
		//MP1_SMN_IH_CREDIT
		#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
		#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10