Unverified Commit bccb5d53 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'memory-controller-drv-5.16-2' of... 

Merge tag 'memory-controller-drv-5.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers

Memory controller drivers for v5.16, part two

1. Convert LPDDR2 bindings to dtschema and extend them with new
   properties.
2. Tegra 20 EMC: support matching timings by LPDDR2 configuration from
   devicetree.

* tag 'memory-controller-drv-5.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  memory: tegra20-emc: Add runtime dependency on devfreq governor module
  memory: tegra20-emc: Support matching timings by LPDDR2 configuration
  memory: Add LPDDR2-info helpers
  dt-bindings: memory: tegra20: emc: Document new LPDDR2 sub-node
  dt-bindings: Add vendor prefix for Elpida Memory
  dt-bindings: memory: lpddr2: Document Elpida B8132B2PB-6D-F
  dt-bindings: memory: lpddr2: Add revision-id properties
  dt-bindings: memory: lpddr2: Convert to schema
  dt-bindings: Relocate DDR bindings

Link: https://lore.kernel.org/r/20211021093002.118192-1-krzysztof.kozlowski@canonical.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents c13d3398 14b43c20

Documentation/devicetree/bindings/ddr/lpddr2.txt

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* LPDDR2 SDRAM memories compliant to JEDEC JESD209-2



Required properties:

- compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2",

  "jedec,lpddr2-s4"



  "ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type



  "ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type



  "ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type



- density  : <u32> representing density in Mb (Mega bits)



- io-width : <u32> representing bus width. Possible values are 8, 16, and 32



Optional properties:



The following optional properties represent the minimum value of some AC

timing parameters of the DDR device in terms of number of clock cycles.

These values shall be obtained from the device data-sheet.

- tRRD-min-tck

- tWTR-min-tck

- tXP-min-tck

- tRTP-min-tck

- tCKE-min-tck

- tRPab-min-tck

- tRCD-min-tck

- tWR-min-tck

- tRASmin-min-tck

- tCKESR-min-tck

- tFAW-min-tck



Child nodes:

- The lpddr2 node may have one or more child nodes of type "lpddr2-timings".

  "lpddr2-timings" provides AC timing parameters of the device for

  a given speed-bin. The user may provide the timings for as many

  speed-bins as is required. Please see Documentation/devicetree/

  bindings/ddr/lpddr2-timings.txt for more information on "lpddr2-timings"



Example:



elpida_ECB240ABACN : lpddr2 {

	compatible	= "Elpida,ECB240ABACN","jedec,lpddr2-s4";

	density		= <2048>;

	io-width	= <32>;



	tRPab-min-tck	= <3>;

	tRCD-min-tck	= <3>;

	tWR-min-tck	= <3>;

	tRASmin-min-tck	= <3>;

	tRRD-min-tck	= <2>;

	tWTR-min-tck	= <2>;

	tXP-min-tck	= <2>;

	tRTP-min-tck	= <2>;

	tCKE-min-tck	= <3>;

	tCKESR-min-tck	= <3>;

	tFAW-min-tck	= <8>;



	timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {

		compatible	= "jedec,lpddr2-timings";

		min-freq	= <10000000>;

		max-freq	= <400000000>;

		tRPab		= <21000>;

		tRCD		= <18000>;

		tWR		= <15000>;

		tRAS-min	= <42000>;

		tRRD		= <10000>;

		tWTR		= <7500>;

		tXP		= <7500>;

		tRTP		= <7500>;

		tCKESR		= <15000>;

		tDQSCK-max	= <5500>;

		tFAW		= <50000>;

		tZQCS		= <90000>;

		tZQCL		= <360000>;

		tZQinit		= <1000000>;

		tRAS-max-ns	= <70000>;

	};



	timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {

		compatible	= "jedec,lpddr2-timings";

		min-freq	= <10000000>;

		max-freq	= <200000000>;

		tRPab		= <21000>;

		tRCD		= <18000>;

		tWR		= <15000>;

		tRAS-min	= <42000>;

		tRRD		= <10000>;

		tWTR		= <10000>;

		tXP		= <7500>;

		tRTP		= <7500>;

		tCKESR		= <15000>;

		tDQSCK-max	= <5500>;

		tFAW		= <50000>;

		tZQCS		= <90000>;

		tZQCL		= <360000>;

		tZQinit		= <1000000>;

		tRAS-max-ns	= <70000>;

	};



}

Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: LPDDR2 SDRAM compliant to JEDEC JESD209-2



maintainers:

  - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>



properties:

  compatible:

    oneOf:

      - items:

          - enum:

              - elpida,ECB240ABACN

              - elpida,B8132B2PB-6D-F

          - enum:

              - jedec,lpddr2-s4

      - items:

          - enum:

              - jedec,lpddr2-s2

      - items:

          - enum:

              - jedec,lpddr2-nvm



  revision-id1:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 255

    description: |

      Revision 1 value of SDRAM chip. Obtained from device datasheet.



  revision-id2:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 255

    description: |

      Revision 2 value of SDRAM chip. Obtained from device datasheet.



  density:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Density in megabits of SDRAM chip. Obtained from device datasheet.

    enum:

      - 64

      - 128

      - 256

      - 512

      - 1024

      - 2048

      - 4096

      - 8192

      - 16384

      - 32768



  io-width:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      IO bus width in bits of SDRAM chip. Obtained from device datasheet.

    enum:

      - 32

      - 16

      - 8



  tRRD-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 16

    description: |

      Active bank a to active bank b in terms of number of clock cycles.

      Obtained from device datasheet.



  tWTR-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 16

    description: |

      Internal WRITE-to-READ command delay in terms of number of clock cycles.

      Obtained from device datasheet.



  tXP-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 16

    description: |

      Exit power-down to next valid command delay in terms of number of clock

      cycles. Obtained from device datasheet.



  tRTP-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 16

    description: |

      Internal READ to PRECHARGE command delay in terms of number of clock

      cycles. Obtained from device datasheet.



  tCKE-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 16

    description: |

      CKE minimum pulse width (HIGH and LOW pulse width) in terms of number

      of clock cycles. Obtained from device datasheet.



  tRPab-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 16

    description: |

      Row precharge time (all banks) in terms of number of clock cycles.

      Obtained from device datasheet.



  tRCD-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 16

    description: |

      RAS-to-CAS delay in terms of number of clock cycles. Obtained from

      device datasheet.



  tWR-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 16

    description: |

      WRITE recovery time in terms of number of clock cycles. Obtained from

      device datasheet.



  tRASmin-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 16

    description: |

      Row active time in terms of number of clock cycles. Obtained from device

      datasheet.



  tCKESR-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 16

    description: |

      CKE minimum pulse width during SELF REFRESH (low pulse width during

      SELF REFRESH) in terms of number of clock cycles. Obtained from device

      datasheet.



  tFAW-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 16

    description: |

      Four-bank activate window in terms of number of clock cycles. Obtained

      from device datasheet.



patternProperties:

  "^lpddr2-timings":

    type: object

    description: |

      The lpddr2 node may have one or more child nodes of type "lpddr2-timings".

      "lpddr2-timings" provides AC timing parameters of the device for

      a given speed-bin. The user may provide the timings for as many

      speed-bins as is required. Please see Documentation/devicetree/

      bindings/memory-controllers/ddr/lpddr2-timings.txt for more information

      on "lpddr2-timings".



required:

  - compatible

  - density

  - io-width



additionalProperties: false



examples:

  - |

    elpida_ECB240ABACN: lpddr2 {

        compatible = "elpida,ECB240ABACN", "jedec,lpddr2-s4";

        density = <2048>;

        io-width = <32>;

        revision-id1 = <1>;

        revision-id2 = <0>;



        tRPab-min-tck = <3>;

        tRCD-min-tck = <3>;

        tWR-min-tck = <3>;

        tRASmin-min-tck = <3>;

        tRRD-min-tck = <2>;

        tWTR-min-tck = <2>;

        tXP-min-tck = <2>;

        tRTP-min-tck = <2>;

        tCKE-min-tck = <3>;

        tCKESR-min-tck = <3>;

        tFAW-min-tck = <8>;



        timings_elpida_ECB240ABACN_400mhz: lpddr2-timings0 {

            compatible = "jedec,lpddr2-timings";

            min-freq = <10000000>;

            max-freq = <400000000>;

            tRPab = <21000>;

            tRCD = <18000>;

            tWR = <15000>;

            tRAS-min = <42000>;

            tRRD = <10000>;

            tWTR = <7500>;

            tXP = <7500>;

            tRTP = <7500>;

            tCKESR = <15000>;

            tDQSCK-max = <5500>;

            tFAW = <50000>;

            tZQCS = <90000>;

            tZQCL = <360000>;

            tZQinit = <1000000>;

            tRAS-max-ns = <70000>;

        };



        timings_elpida_ECB240ABACN_200mhz: lpddr2-timings1 {

            compatible = "jedec,lpddr2-timings";

            min-freq = <10000000>;

            max-freq = <200000000>;

            tRPab = <21000>;

            tRCD = <18000>;

            tWR = <15000>;

            tRAS-min = <42000>;

            tRRD = <10000>;

            tWTR = <10000>;

            tXP = <7500>;

            tRTP = <7500>;

            tCKESR = <15000>;

            tDQSCK-max = <5500>;

            tFAW = <50000>;

            tZQCS = <90000>;

            tZQCL = <360000>;

            tZQinit = <1000000>;

            tRAS-max-ns = <70000>;

        };

    };

Documentation/devicetree/bindings/ddr/lpddr3.txt→Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt

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@@ -43,8 +43,9 @@ These values shall be obtained from the device data-sheet. 
Child nodes:

- The lpddr3 node may have one or more child nodes of type "lpddr3-timings".

  "lpddr3-timings" provides AC timing parameters of the device for

  a given speed-bin. Please see Documentation/devicetree/

  bindings/ddr/lpddr3-timings.txt for more information on "lpddr3-timings"

  a given speed-bin. Please see

  Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt

  for more information on "lpddr3-timings"



Example: