Commit bcababfc authored by Ilpo Järvinen's avatar Ilpo Järvinen Committed by Lee Jones
Browse files

mfd: intel-m10-bmc: Prefix register defines with M10BMC_N3000 



Prefix the M10BMC defines register defines with M10BMC_N3000 to make it
more obvious these are related to some board type. All current
non-N3000 board types have the same layout so they'll be reused. The
less generic makes it more obvious they're not meant for the
generic/interface agnostic code.

Reviewed-by: default avatarRuss Weight <russell.h.weight@intel.com>
Reviewed-by: default avatarXu Yilun <yilun.xu@intel.com>
Signed-off-by: default avatarIlpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: default avatarLee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20230116100845.6153-8-ilpo.jarvinen@linux.intel.com
parent 3e10c805

drivers/mfd/intel-m10-bmc-core.c

+7 −7
Original line number Original line Diff line number Diff line
@@ -58,12 +58,12 @@ static ssize_t mac_address_show(struct device *dev, 
		return ret;

		return ret;





	return sysfs_emit(buf, "%02x:%02x:%02x:%02x:%02x:%02x\n",

	return sysfs_emit(buf, "%02x:%02x:%02x:%02x:%02x:%02x\n",

			  (u8)FIELD_GET(M10BMC_MAC_BYTE1, macaddr_low),

			  (u8)FIELD_GET(M10BMC_N3000_MAC_BYTE1, macaddr_low),

			  (u8)FIELD_GET(M10BMC_MAC_BYTE2, macaddr_low),

			  (u8)FIELD_GET(M10BMC_N3000_MAC_BYTE2, macaddr_low),

			  (u8)FIELD_GET(M10BMC_MAC_BYTE3, macaddr_low),

			  (u8)FIELD_GET(M10BMC_N3000_MAC_BYTE3, macaddr_low),

			  (u8)FIELD_GET(M10BMC_MAC_BYTE4, macaddr_low),

			  (u8)FIELD_GET(M10BMC_N3000_MAC_BYTE4, macaddr_low),

			  (u8)FIELD_GET(M10BMC_MAC_BYTE5, macaddr_high),

			  (u8)FIELD_GET(M10BMC_N3000_MAC_BYTE5, macaddr_high),

			  (u8)FIELD_GET(M10BMC_MAC_BYTE6, macaddr_high));

			  (u8)FIELD_GET(M10BMC_N3000_MAC_BYTE6, macaddr_high));

}

}

static DEVICE_ATTR_RO(mac_address);

static DEVICE_ATTR_RO(mac_address);
@@ -78,7 +78,7 @@ static ssize_t mac_count_show(struct device *dev, 
	if (ret)

	if (ret)

		return ret;

		return ret;





	return sysfs_emit(buf, "%u\n", (u8)FIELD_GET(M10BMC_MAC_COUNT, macaddr_high));

	return sysfs_emit(buf, "%u\n", (u8)FIELD_GET(M10BMC_N3000_MAC_COUNT, macaddr_high));

}

}

static DEVICE_ATTR_RO(mac_count);

static DEVICE_ATTR_RO(mac_count);

drivers/mfd/intel-m10-bmc-spi.c

+26 −26
Original line number Original line Diff line number Diff line
@@ -14,9 +14,9 @@ 
#include <linux/spi/spi.h>

#include <linux/spi/spi.h>





static const struct regmap_range m10bmc_regmap_range[] = {

static const struct regmap_range m10bmc_regmap_range[] = {

	regmap_reg_range(M10BMC_LEGACY_BUILD_VER, M10BMC_LEGACY_BUILD_VER),

	regmap_reg_range(M10BMC_N3000_LEGACY_BUILD_VER, M10BMC_N3000_LEGACY_BUILD_VER),

	regmap_reg_range(M10BMC_SYS_BASE, M10BMC_SYS_END),

	regmap_reg_range(M10BMC_N3000_SYS_BASE, M10BMC_N3000_SYS_END),

	regmap_reg_range(M10BMC_FLASH_BASE, M10BMC_FLASH_END),

	regmap_reg_range(M10BMC_N3000_FLASH_BASE, M10BMC_N3000_FLASH_END),

};

};





static const struct regmap_access_table m10bmc_access_table = {

static const struct regmap_access_table m10bmc_access_table = {
@@ -30,7 +30,7 @@ static struct regmap_config intel_m10bmc_regmap_config = { 
	.reg_stride = 4,

	.reg_stride = 4,

	.wr_table = &m10bmc_access_table,

	.wr_table = &m10bmc_access_table,

	.rd_table = &m10bmc_access_table,

	.rd_table = &m10bmc_access_table,

	.max_register = M10BMC_MEM_END,

	.max_register = M10BMC_N3000_MEM_END,

};

};





static int check_m10bmc_version(struct intel_m10bmc *ddata)

static int check_m10bmc_version(struct intel_m10bmc *ddata)
@@ -41,16 +41,16 @@ static int check_m10bmc_version(struct intel_m10bmc *ddata) 
	/*

	/*

	 * This check is to filter out the very old legacy BMC versions. In the

	 * This check is to filter out the very old legacy BMC versions. In the

	 * old BMC chips, the BMC version info is stored in the old version

	 * old BMC chips, the BMC version info is stored in the old version

	 * register (M10BMC_LEGACY_BUILD_VER), so its read out value would have

	 * register (M10BMC_N3000_LEGACY_BUILD_VER), so its read out value would have

	 * not been M10BMC_VER_LEGACY_INVALID (0xffffffff). But in new BMC

	 * not been M10BMC_N3000_VER_LEGACY_INVALID (0xffffffff). But in new BMC

	 * chips that the driver supports, the value of this register should be

	 * chips that the driver supports, the value of this register should be

	 * M10BMC_VER_LEGACY_INVALID.

	 * M10BMC_N3000_VER_LEGACY_INVALID.

	 */

	 */

	ret = m10bmc_raw_read(ddata, M10BMC_LEGACY_BUILD_VER, &v);

	ret = m10bmc_raw_read(ddata, M10BMC_N3000_LEGACY_BUILD_VER, &v);

	if (ret)

	if (ret)

		return -ENODEV;

		return -ENODEV;





	if (v != M10BMC_VER_LEGACY_INVALID) {

	if (v != M10BMC_N3000_VER_LEGACY_INVALID) {

		dev_err(ddata->dev, "bad version M10BMC detected\n");

		dev_err(ddata->dev, "bad version M10BMC detected\n");

		return -ENODEV;

		return -ENODEV;

	}

	}
@@ -92,23 +92,23 @@ static int intel_m10_bmc_spi_probe(struct spi_device *spi) 
}

}





static const struct m10bmc_csr_map m10bmc_n3000_csr_map = {

static const struct m10bmc_csr_map m10bmc_n3000_csr_map = {

	.base = M10BMC_SYS_BASE,

	.base = M10BMC_N3000_SYS_BASE,

	.build_version = M10BMC_BUILD_VER,

	.build_version = M10BMC_N3000_BUILD_VER,

	.fw_version = NIOS2_FW_VERSION,

	.fw_version = NIOS2_N3000_FW_VERSION,

	.mac_low = M10BMC_MAC_LOW,

	.mac_low = M10BMC_N3000_MAC_LOW,

	.mac_high = M10BMC_MAC_HIGH,

	.mac_high = M10BMC_N3000_MAC_HIGH,

	.doorbell = M10BMC_DOORBELL,

	.doorbell = M10BMC_N3000_DOORBELL,

	.auth_result = M10BMC_AUTH_RESULT,

	.auth_result = M10BMC_N3000_AUTH_RESULT,

	.bmc_prog_addr = BMC_PROG_ADDR,

	.bmc_prog_addr = M10BMC_N3000_BMC_PROG_ADDR,

	.bmc_reh_addr = BMC_REH_ADDR,

	.bmc_reh_addr = M10BMC_N3000_BMC_REH_ADDR,

	.bmc_magic = BMC_PROG_MAGIC,

	.bmc_magic = M10BMC_N3000_BMC_PROG_MAGIC,

	.sr_prog_addr = SR_PROG_ADDR,

	.sr_prog_addr = M10BMC_N3000_SR_PROG_ADDR,

	.sr_reh_addr = SR_REH_ADDR,

	.sr_reh_addr = M10BMC_N3000_SR_REH_ADDR,

	.sr_magic = SR_PROG_MAGIC,

	.sr_magic = M10BMC_N3000_SR_PROG_MAGIC,

	.pr_prog_addr = PR_PROG_ADDR,

	.pr_prog_addr = M10BMC_N3000_PR_PROG_ADDR,

	.pr_reh_addr = PR_REH_ADDR,

	.pr_reh_addr = M10BMC_N3000_PR_REH_ADDR,

	.pr_magic = PR_PROG_MAGIC,

	.pr_magic = M10BMC_N3000_PR_PROG_MAGIC,

	.rsu_update_counter = STAGING_FLASH_COUNT,

	.rsu_update_counter = M10BMC_N3000_STAGING_FLASH_COUNT,

};

};





static struct mfd_cell m10bmc_d5005_subdevs[] = {

static struct mfd_cell m10bmc_d5005_subdevs[] = {

include/linux/mfd/intel-m10-bmc.h

+33 −33
Original line number Original line Diff line number Diff line
@@ -12,38 +12,38 @@ 
#include <linux/dev_printk.h>

#include <linux/dev_printk.h>

#include <linux/regmap.h>

#include <linux/regmap.h>





#define M10BMC_LEGACY_BUILD_VER		0x300468

#define M10BMC_N3000_LEGACY_BUILD_VER	0x300468

#define M10BMC_SYS_BASE			0x300800

#define M10BMC_N3000_SYS_BASE		0x300800

#define M10BMC_SYS_END			0x300fff

#define M10BMC_N3000_SYS_END		0x300fff

#define M10BMC_FLASH_BASE		0x10000000

#define M10BMC_N3000_FLASH_BASE		0x10000000

#define M10BMC_FLASH_END		0x1fffffff

#define M10BMC_N3000_FLASH_END		0x1fffffff

#define M10BMC_MEM_END			M10BMC_FLASH_END

#define M10BMC_N3000_MEM_END		M10BMC_N3000_FLASH_END





#define M10BMC_STAGING_BASE		0x18000000

#define M10BMC_STAGING_BASE		0x18000000

#define M10BMC_STAGING_SIZE		0x3800000

#define M10BMC_STAGING_SIZE		0x3800000





/* Register offset of system registers */

/* Register offset of system registers */

#define NIOS2_FW_VERSION		0x0

#define NIOS2_N3000_FW_VERSION		0x0

#define M10BMC_MAC_LOW			0x10

#define M10BMC_N3000_MAC_LOW		0x10

#define M10BMC_MAC_BYTE4		GENMASK(7, 0)

#define M10BMC_N3000_MAC_BYTE4		GENMASK(7, 0)

#define M10BMC_MAC_BYTE3		GENMASK(15, 8)

#define M10BMC_N3000_MAC_BYTE3		GENMASK(15, 8)

#define M10BMC_MAC_BYTE2		GENMASK(23, 16)

#define M10BMC_N3000_MAC_BYTE2		GENMASK(23, 16)

#define M10BMC_MAC_BYTE1		GENMASK(31, 24)

#define M10BMC_N3000_MAC_BYTE1		GENMASK(31, 24)

#define M10BMC_MAC_HIGH			0x14

#define M10BMC_N3000_MAC_HIGH		0x14

#define M10BMC_MAC_BYTE6		GENMASK(7, 0)

#define M10BMC_N3000_MAC_BYTE6		GENMASK(7, 0)

#define M10BMC_MAC_BYTE5		GENMASK(15, 8)

#define M10BMC_N3000_MAC_BYTE5		GENMASK(15, 8)

#define M10BMC_MAC_COUNT		GENMASK(23, 16)

#define M10BMC_N3000_MAC_COUNT		GENMASK(23, 16)

#define M10BMC_TEST_REG			0x3c

#define M10BMC_N3000_TEST_REG		0x3c

#define M10BMC_BUILD_VER		0x68

#define M10BMC_N3000_BUILD_VER		0x68

#define M10BMC_VER_MAJOR_MSK		GENMASK(23, 16)

#define M10BMC_N3000_VER_MAJOR_MSK	GENMASK(23, 16)

#define M10BMC_VER_PCB_INFO_MSK		GENMASK(31, 24)

#define M10BMC_N3000_VER_PCB_INFO_MSK	GENMASK(31, 24)

#define M10BMC_VER_LEGACY_INVALID	0xffffffff

#define M10BMC_N3000_VER_LEGACY_INVALID	0xffffffff





/* Secure update doorbell register, in system register region */

/* Secure update doorbell register, in system register region */

#define M10BMC_DOORBELL			0x400

#define M10BMC_N3000_DOORBELL		0x400





/* Authorization Result register, in system register region */

/* Authorization Result register, in system register region */

#define M10BMC_AUTH_RESULT		0x404

#define M10BMC_N3000_AUTH_RESULT		0x404





/* Doorbell register fields */

/* Doorbell register fields */

#define DRBL_RSU_REQUEST		BIT(0)

#define DRBL_RSU_REQUEST		BIT(0)
@@ -106,20 +106,20 @@ 
#define RSU_COMPLETE_TIMEOUT_MS		(40 * 60 * 1000)

#define RSU_COMPLETE_TIMEOUT_MS		(40 * 60 * 1000)





/* Addresses for security related data in FLASH */

/* Addresses for security related data in FLASH */

#define BMC_REH_ADDR	0x17ffc004

#define M10BMC_N3000_BMC_REH_ADDR	0x17ffc004

#define BMC_PROG_ADDR	0x17ffc000

#define M10BMC_N3000_BMC_PROG_ADDR	0x17ffc000

#define BMC_PROG_MAGIC	0x5746

#define M10BMC_N3000_BMC_PROG_MAGIC	0x5746





#define SR_REH_ADDR	0x17ffd004

#define M10BMC_N3000_SR_REH_ADDR	0x17ffd004

#define SR_PROG_ADDR	0x17ffd000

#define M10BMC_N3000_SR_PROG_ADDR	0x17ffd000

#define SR_PROG_MAGIC	0x5253

#define M10BMC_N3000_SR_PROG_MAGIC	0x5253





#define PR_REH_ADDR	0x17ffe004

#define M10BMC_N3000_PR_REH_ADDR	0x17ffe004

#define PR_PROG_ADDR	0x17ffe000

#define M10BMC_N3000_PR_PROG_ADDR	0x17ffe000

#define PR_PROG_MAGIC	0x5250

#define M10BMC_N3000_PR_PROG_MAGIC	0x5250





/* Address of 4KB inverted bit vector containing staging area FLASH count */

/* Address of 4KB inverted bit vector containing staging area FLASH count */

#define STAGING_FLASH_COUNT	0x17ffb000

#define M10BMC_N3000_STAGING_FLASH_COUNT	0x17ffb000





/**

/**

 * struct m10bmc_csr_map - Intel MAX 10 BMC CSR register map

 * struct m10bmc_csr_map - Intel MAX 10 BMC CSR register map