Commit bc84ee94 authored by Neil Armstrong's avatar Neil Armstrong
Browse files

drm/meson: crtc: handle commit of Amlogic FBC frames 



Since the VD1 Amlogic FBC decoder is now configured by the overlay driver,
commit the right registers to decode the Amlogic FBC frame.

Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Tested-by: default avatarKevin Hilman <khilman@baylibre.com>
Reviewed-by: default avatarKevin Hilman <khilman@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200703080728.25207-7-narmstrong@baylibre.com
parent be26a04b

drivers/gpu/drm/meson/meson_crtc.c

+88 −30
Original line number Diff line number Diff line
@@ -291,6 +291,10 @@ static void meson_crtc_enable_vd1(struct meson_drm *priv) 
			    VPP_VD1_PREBLEND | VPP_VD1_POSTBLEND |

			    VPP_COLOR_MNG_ENABLE,

			    priv->io_base + _REG(VPP_MISC));



	writel_bits_relaxed(VIU_CTRL0_AFBC_TO_VD1,

			    priv->viu.vd1_afbc ? VIU_CTRL0_AFBC_TO_VD1 : 0,

			    priv->io_base + _REG(VIU_MISC_CTRL0));

}



static void meson_g12a_crtc_enable_vd1(struct meson_drm *priv)
@@ -300,6 +304,10 @@ static void meson_g12a_crtc_enable_vd1(struct meson_drm *priv) 
		       VD_BLEND_POSTBLD_SRC_VD1 |

		       VD_BLEND_POSTBLD_PREMULT_EN,

		       priv->io_base + _REG(VD1_BLEND_SRC_CTRL));



	writel_relaxed(priv->viu.vd1_afbc ?

		       (VD1_AXI_SEL_AFBC | AFBC_VD1_SEL) : 0,

		       priv->io_base + _REG(VD1_AFBCD0_MISC_CTRL));

}



void meson_crtc_irq(struct meson_drm *priv)
@@ -383,6 +391,53 @@ void meson_crtc_irq(struct meson_drm *priv) 
	/* Update the VD1 registers */

	if (priv->viu.vd1_enabled && priv->viu.vd1_commit) {



		if (priv->viu.vd1_afbc) {

			writel_relaxed(priv->viu.vd1_afbc_head_addr,

				       priv->io_base +

				       _REG(AFBC_HEAD_BADDR));

			writel_relaxed(priv->viu.vd1_afbc_body_addr,

				       priv->io_base +

				       _REG(AFBC_BODY_BADDR));

			writel_relaxed(priv->viu.vd1_afbc_en,

				       priv->io_base +

				       _REG(AFBC_ENABLE));

			writel_relaxed(priv->viu.vd1_afbc_mode,

				       priv->io_base +

				       _REG(AFBC_MODE));

			writel_relaxed(priv->viu.vd1_afbc_size_in,

				       priv->io_base +

				       _REG(AFBC_SIZE_IN));

			writel_relaxed(priv->viu.vd1_afbc_dec_def_color,

				       priv->io_base +

				       _REG(AFBC_DEC_DEF_COLOR));

			writel_relaxed(priv->viu.vd1_afbc_conv_ctrl,

				       priv->io_base +

				       _REG(AFBC_CONV_CTRL));

			writel_relaxed(priv->viu.vd1_afbc_size_out,

				       priv->io_base +

				       _REG(AFBC_SIZE_OUT));

			writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_ctrl,

				       priv->io_base +

				       _REG(AFBC_VD_CFMT_CTRL));

			writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_w,

				       priv->io_base +

				       _REG(AFBC_VD_CFMT_W));

			writel_relaxed(priv->viu.vd1_afbc_mif_hor_scope,

				       priv->io_base +

				       _REG(AFBC_MIF_HOR_SCOPE));

			writel_relaxed(priv->viu.vd1_afbc_mif_ver_scope,

				       priv->io_base +

				       _REG(AFBC_MIF_VER_SCOPE));

			writel_relaxed(priv->viu.vd1_afbc_pixel_hor_scope,

				       priv->io_base+

				       _REG(AFBC_PIXEL_HOR_SCOPE));

			writel_relaxed(priv->viu.vd1_afbc_pixel_ver_scope,

				       priv->io_base +

				       _REG(AFBC_PIXEL_VER_SCOPE));

			writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_h,

				       priv->io_base +

				       _REG(AFBC_VD_CFMT_H));

		} else {

			switch (priv->viu.vd1_planes) {

			case 3:

				meson_canvas_config(priv->canvas,
@@ -393,7 +448,7 @@ void meson_crtc_irq(struct meson_drm *priv) 
						    MESON_CANVAS_WRAP_NONE,

						    MESON_CANVAS_BLKMODE_LINEAR,

						    MESON_CANVAS_ENDIAN_SWAP64);

		/* fallthrough */

				fallthrough;

			case 2:

				meson_canvas_config(priv->canvas,

						    priv->canvas_id_vd1_1,
@@ -403,7 +458,7 @@ void meson_crtc_irq(struct meson_drm *priv) 
						    MESON_CANVAS_WRAP_NONE,

						    MESON_CANVAS_BLKMODE_LINEAR,

						    MESON_CANVAS_ENDIAN_SWAP64);

		/* fallthrough */

				fallthrough;

			case 1:

				meson_canvas_config(priv->canvas,

						    priv->canvas_id_vd1_0,
@@ -415,6 +470,9 @@ void meson_crtc_irq(struct meson_drm *priv) 
						    MESON_CANVAS_ENDIAN_SWAP64);

			}



			writel_relaxed(0, priv->io_base + _REG(AFBC_ENABLE));

		}



		writel_relaxed(priv->viu.vd1_if0_gen_reg,

				priv->io_base + meson_crtc->viu_offset +

				_REG(VD1_IF0_GEN_REG));