Loading arch/arm/boot/dts/am335x-icev2.dts +1 −1 Original line number Diff line number Diff line Loading @@ -432,7 +432,7 @@ pinctrl-0 = <&mmc0_pins_default>; }; &gpio0 { &gpio0_target { /* Do not idle the GPIO used for holding the VTT regulator */ ti,no-reset-on-init; ti,no-idle-on-init; Loading arch/arm/boot/dts/am33xx-l4.dtsi +4 −2 Original line number Diff line number Diff line Loading @@ -127,7 +127,7 @@ ranges = <0x0 0x5000 0x1000>; }; target-module@7000 { /* 0x44e07000, ap 14 20.0 */ gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "gpio1"; reg = <0x7000 0x4>, Loading Loading @@ -2038,7 +2038,9 @@ reg = <0xe000 0x4>, <0xe054 0x4>; reg-names = "rev", "sysc"; ti,sysc-midle ; ti,sysc-midle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>; Loading arch/arm/boot/dts/am3874-iceboard.dts +1 −8 Original line number Diff line number Diff line Loading @@ -111,13 +111,13 @@ reg = <0x70>; #address-cells = <1>; #size-cells = <0>; i2c-mux-idle-disconnect; i2c@0 { /* FMC A */ #address-cells = <1>; #size-cells = <0>; reg = <0>; i2c-mux-idle-disconnect; }; i2c@1 { Loading @@ -125,7 +125,6 @@ #address-cells = <1>; #size-cells = <0>; reg = <1>; i2c-mux-idle-disconnect; }; i2c@2 { Loading @@ -133,7 +132,6 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; i2c-mux-idle-disconnect; }; i2c@3 { Loading @@ -141,7 +139,6 @@ #address-cells = <1>; #size-cells = <0>; reg = <3>; i2c-mux-idle-disconnect; }; i2c@4 { Loading @@ -149,14 +146,12 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; i2c-mux-idle-disconnect; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; i2c-mux-idle-disconnect; ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <5000>; }; ina230@41 { compatible = "ti,ina230"; reg = <0x41>; shunt-resistor = <5000>; }; Loading @@ -182,14 +177,12 @@ #address-cells = <1>; #size-cells = <0>; reg = <6>; i2c-mux-idle-disconnect; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; i2c-mux-idle-disconnect; u41: pca9575@20 { compatible = "nxp,pca9575"; Loading arch/arm/boot/dts/am4372.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -337,6 +337,8 @@ ti,hwmods = "dss_dispc"; clocks = <&disp_clk>; clock-names = "fck"; max-memory-bandwidth = <230000000>; }; rfbi: rfbi@4832a800 { Loading arch/arm/boot/dts/dra7-l4.dtsi +21 −27 Original line number Diff line number Diff line Loading @@ -2732,7 +2732,7 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; dma-names = "tx", "rx"; clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 22>, clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>, <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; clock-names = "fck", "ahclkx", "ahclkr"; Loading Loading @@ -2768,8 +2768,8 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; dma-names = "tx", "rx"; clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 22>, <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>, <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; clock-names = "fck", "ahclkx", "ahclkr"; status = "disabled"; Loading @@ -2786,9 +2786,8 @@ <SYSC_IDLE_SMART>; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 28>; clock-names = "fck", "ahclkx", "ahclkr"; <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; clock-names = "fck", "ahclkx"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x68000 0x2000>, Loading @@ -2804,7 +2803,7 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; dma-names = "tx", "rx"; clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 22>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; Loading @@ -2821,9 +2820,8 @@ <SYSC_IDLE_SMART>; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 28>; clock-names = "fck", "ahclkx", "ahclkr"; <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; clock-names = "fck", "ahclkx"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6c000 0x2000>, Loading @@ -2839,7 +2837,7 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; dma-names = "tx", "rx"; clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 22>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; Loading @@ -2856,9 +2854,8 @@ <SYSC_IDLE_SMART>; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 28>; clock-names = "fck", "ahclkx", "ahclkr"; <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; clock-names = "fck", "ahclkx"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x70000 0x2000>, Loading @@ -2874,7 +2871,7 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; dma-names = "tx", "rx"; clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 22>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; Loading @@ -2891,9 +2888,8 @@ <SYSC_IDLE_SMART>; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 28>; clock-names = "fck", "ahclkx", "ahclkr"; <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; clock-names = "fck", "ahclkx"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x74000 0x2000>, Loading @@ -2909,7 +2905,7 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; dma-names = "tx", "rx"; clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 22>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; Loading @@ -2926,9 +2922,8 @@ <SYSC_IDLE_SMART>; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 28>; clock-names = "fck", "ahclkx", "ahclkr"; <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; clock-names = "fck", "ahclkx"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x78000 0x2000>, Loading @@ -2944,7 +2939,7 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; dma-names = "tx", "rx"; clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 22>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; Loading @@ -2961,9 +2956,8 @@ <SYSC_IDLE_SMART>; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 28>; clock-names = "fck", "ahclkx", "ahclkr"; <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; clock-names = "fck", "ahclkx"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x7c000 0x2000>, Loading @@ -2979,7 +2973,7 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; dma-names = "tx", "rx"; clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 22>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; Loading Loading
arch/arm/boot/dts/am335x-icev2.dts +1 −1 Original line number Diff line number Diff line Loading @@ -432,7 +432,7 @@ pinctrl-0 = <&mmc0_pins_default>; }; &gpio0 { &gpio0_target { /* Do not idle the GPIO used for holding the VTT regulator */ ti,no-reset-on-init; ti,no-idle-on-init; Loading
arch/arm/boot/dts/am33xx-l4.dtsi +4 −2 Original line number Diff line number Diff line Loading @@ -127,7 +127,7 @@ ranges = <0x0 0x5000 0x1000>; }; target-module@7000 { /* 0x44e07000, ap 14 20.0 */ gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "gpio1"; reg = <0x7000 0x4>, Loading Loading @@ -2038,7 +2038,9 @@ reg = <0xe000 0x4>, <0xe054 0x4>; reg-names = "rev", "sysc"; ti,sysc-midle ; ti,sysc-midle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>; Loading
arch/arm/boot/dts/am3874-iceboard.dts +1 −8 Original line number Diff line number Diff line Loading @@ -111,13 +111,13 @@ reg = <0x70>; #address-cells = <1>; #size-cells = <0>; i2c-mux-idle-disconnect; i2c@0 { /* FMC A */ #address-cells = <1>; #size-cells = <0>; reg = <0>; i2c-mux-idle-disconnect; }; i2c@1 { Loading @@ -125,7 +125,6 @@ #address-cells = <1>; #size-cells = <0>; reg = <1>; i2c-mux-idle-disconnect; }; i2c@2 { Loading @@ -133,7 +132,6 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; i2c-mux-idle-disconnect; }; i2c@3 { Loading @@ -141,7 +139,6 @@ #address-cells = <1>; #size-cells = <0>; reg = <3>; i2c-mux-idle-disconnect; }; i2c@4 { Loading @@ -149,14 +146,12 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; i2c-mux-idle-disconnect; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; i2c-mux-idle-disconnect; ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <5000>; }; ina230@41 { compatible = "ti,ina230"; reg = <0x41>; shunt-resistor = <5000>; }; Loading @@ -182,14 +177,12 @@ #address-cells = <1>; #size-cells = <0>; reg = <6>; i2c-mux-idle-disconnect; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; i2c-mux-idle-disconnect; u41: pca9575@20 { compatible = "nxp,pca9575"; Loading
arch/arm/boot/dts/am4372.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -337,6 +337,8 @@ ti,hwmods = "dss_dispc"; clocks = <&disp_clk>; clock-names = "fck"; max-memory-bandwidth = <230000000>; }; rfbi: rfbi@4832a800 { Loading
arch/arm/boot/dts/dra7-l4.dtsi +21 −27 Original line number Diff line number Diff line Loading @@ -2732,7 +2732,7 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; dma-names = "tx", "rx"; clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 22>, clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>, <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; clock-names = "fck", "ahclkx", "ahclkr"; Loading Loading @@ -2768,8 +2768,8 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; dma-names = "tx", "rx"; clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 22>, <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>, <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; clock-names = "fck", "ahclkx", "ahclkr"; status = "disabled"; Loading @@ -2786,9 +2786,8 @@ <SYSC_IDLE_SMART>; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 28>; clock-names = "fck", "ahclkx", "ahclkr"; <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; clock-names = "fck", "ahclkx"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x68000 0x2000>, Loading @@ -2804,7 +2803,7 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; dma-names = "tx", "rx"; clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 22>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; Loading @@ -2821,9 +2820,8 @@ <SYSC_IDLE_SMART>; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 28>; clock-names = "fck", "ahclkx", "ahclkr"; <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; clock-names = "fck", "ahclkx"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6c000 0x2000>, Loading @@ -2839,7 +2837,7 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; dma-names = "tx", "rx"; clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 22>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; Loading @@ -2856,9 +2854,8 @@ <SYSC_IDLE_SMART>; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 28>; clock-names = "fck", "ahclkx", "ahclkr"; <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; clock-names = "fck", "ahclkx"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x70000 0x2000>, Loading @@ -2874,7 +2871,7 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; dma-names = "tx", "rx"; clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 22>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; Loading @@ -2891,9 +2888,8 @@ <SYSC_IDLE_SMART>; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 28>; clock-names = "fck", "ahclkx", "ahclkr"; <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; clock-names = "fck", "ahclkx"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x74000 0x2000>, Loading @@ -2909,7 +2905,7 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; dma-names = "tx", "rx"; clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 22>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; Loading @@ -2926,9 +2922,8 @@ <SYSC_IDLE_SMART>; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 28>; clock-names = "fck", "ahclkx", "ahclkr"; <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; clock-names = "fck", "ahclkx"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x78000 0x2000>, Loading @@ -2944,7 +2939,7 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; dma-names = "tx", "rx"; clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 22>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; Loading @@ -2961,9 +2956,8 @@ <SYSC_IDLE_SMART>; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 28>; clock-names = "fck", "ahclkx", "ahclkr"; <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; clock-names = "fck", "ahclkx"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x7c000 0x2000>, Loading @@ -2979,7 +2973,7 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; dma-names = "tx", "rx"; clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 22>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; Loading