Commit bc6f4921 authored by Rafael J. Wysocki's avatar Rafael J. Wysocki
Browse files

Merge tag 'devfreq-next-for-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux 

Pull devfreq material for v5.14 from Chanwoo Choi:

 1. Update devfreq core

  - Use DEVICE_ATTR_RW macro for devfreq userspace governor.

  - Add missing error code in devfreq_add_device().

  - Fix get_target_freq() when not using required-opp.

2. Update devfreq drivers

  - Remove unneeded get_dev_status() and polling_ms from imx-bus.c,
    because imx-bus.c doesn't support simple_ondemand.

  - Remove unneeded DEVFREQ_GOV_SIMPLE_ONDEMAND dependecy from
    imx8m-ddrc.c, because it doesn't support the simple_ondemand
    governor.

  - Use tegra30-devfreq.c as thermal cooling device.

  - Convert dt-binding doc style to yaml and add cooling-cells
    property information to dt-binding doc for tegra30-devfreq.c.

* tag 'devfreq-next-for-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux:
  PM / devfreq: passive: Fix get_target_freq when not using required-opp
  dt-bindings: devfreq: tegra30-actmon: Add cooling-cells
  dt-bindings: devfreq: tegra30-actmon: Convert to schema
  PM / devfreq: userspace: Use DEVICE_ATTR_RW macro
  PM / devfreq: imx8m-ddrc: Remove DEVFREQ_GOV_SIMPLE_ONDEMAND dependency
  PM / devfreq: tegra30: Support thermal cooling
  PM / devfreq: imx-bus: Remove imx_bus_get_dev_status
  PM / devfreq: Add missing error code in devfreq_add_device()
parents 13311e74 8c37d01e

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt

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NVIDIA Tegra Activity Monitor



The activity monitor block collects statistics about the behaviour of other

components in the system. This information can be used to derive the rate at

which the external memory needs to be clocked in order to serve all requests

from the monitored clients.



Required properties:

- compatible: should be "nvidia,tegra<chip>-actmon"

- reg: offset and length of the register set for the device

- interrupts: standard interrupt property

- clocks: Must contain a phandle and clock specifier pair for each entry in

clock-names. See ../../clock/clock-bindings.txt for details.

- clock-names: Must include the following entries:

  - actmon

  - emc

- resets: Must contain an entry for each entry in reset-names. See

../../reset/reset.txt for details.

- reset-names: Must include the following entries:

  - actmon

- operating-points-v2: See ../bindings/opp/opp.txt for details.

- interconnects: Should contain entries for memory clients sitting on

                 MC->EMC memory interconnect path.

- interconnect-names: Should include name of the interconnect path for each

                      interconnect entry. Consult TRM documentation for

                      information about available memory clients, see MEMORY

                      CONTROLLER section.



For each opp entry in 'operating-points-v2' table:

- opp-supported-hw: bitfield indicating SoC speedo ID mask

- opp-peak-kBps: peak bandwidth of the memory channel



Example:

	dfs_opp_table: opp-table {

		compatible = "operating-points-v2";



		opp@12750000 {

			opp-hz = /bits/ 64 <12750000>;

			opp-supported-hw = <0x000F>;

			opp-peak-kBps = <51000>;

		};

		...

	};



	actmon@6000c800 {

		compatible = "nvidia,tegra124-actmon";

		reg = <0x0 0x6000c800 0x0 0x400>;

		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&tegra_car TEGRA124_CLK_ACTMON>,

			 <&tegra_car TEGRA124_CLK_EMC>;

		clock-names = "actmon", "emc";

		resets = <&tegra_car 119>;

		reset-names = "actmon";

		operating-points-v2 = <&dfs_opp_table>;

		interconnects = <&mc TEGRA124_MC_MPCORER &emc>;

		interconnect-names = "cpu";

	};

Documentation/devicetree/bindings/devfreq/nvidia,tegra30-actmon.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/devfreq/nvidia,tegra30-actmon.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: NVIDIA Tegra30 Activity Monitor



maintainers:

  - Dmitry Osipenko <digetx@gmail.com>

  - Jon Hunter <jonathanh@nvidia.com>

  - Thierry Reding <thierry.reding@gmail.com>



description: |

  The activity monitor block collects statistics about the behaviour of other

  components in the system. This information can be used to derive the rate at

  which the external memory needs to be clocked in order to serve all requests

  from the monitored clients.



properties:

  compatible:

    enum:

      - nvidia,tegra30-actmon

      - nvidia,tegra114-actmon

      - nvidia,tegra124-actmon

      - nvidia,tegra210-actmon



  reg:

    maxItems: 1



  clocks:

    maxItems: 2



  clock-names:

    items:

      - const: actmon

      - const: emc



  resets:

    maxItems: 1



  reset-names:

    items:

      - const: actmon



  interrupts:

    maxItems: 1



  interconnects:

    minItems: 1

    maxItems: 12



  interconnect-names:

    minItems: 1

    maxItems: 12

    description:

      Should include name of the interconnect path for each interconnect

      entry. Consult TRM documentation for information about available

      memory clients, see MEMORY CONTROLLER and ACTIVITY MONITOR sections.



  operating-points-v2:

    description:

      Should contain freqs and voltages and opp-supported-hw property, which

      is a bitfield indicating SoC speedo ID mask.



  "#cooling-cells":

    const: 2



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - resets

  - reset-names

  - interrupts

  - interconnects

  - interconnect-names

  - operating-points-v2

  - "#cooling-cells"



additionalProperties: false



examples:

  - |

    #include <dt-bindings/memory/tegra30-mc.h>



    mc: memory-controller@7000f000 {

        compatible = "nvidia,tegra30-mc";

        reg = <0x7000f000 0x400>;

        clocks = <&clk 32>;

        clock-names = "mc";



        interrupts = <0 77 4>;



        #iommu-cells = <1>;

        #reset-cells = <1>;

        #interconnect-cells = <1>;

    };



    emc: external-memory-controller@7000f400 {

        compatible = "nvidia,tegra30-emc";

        reg = <0x7000f400 0x400>;

        interrupts = <0 78 4>;

        clocks = <&clk 57>;



        nvidia,memory-controller = <&mc>;

        operating-points-v2 = <&dvfs_opp_table>;

        power-domains = <&domain>;



        #interconnect-cells = <0>;

    };



    actmon@6000c800 {

        compatible = "nvidia,tegra30-actmon";

        reg = <0x6000c800 0x400>;

        interrupts = <0 45 4>;

        clocks = <&clk 119>, <&clk 57>;

        clock-names = "actmon", "emc";

        resets = <&rst 119>;

        reset-names = "actmon";

        operating-points-v2 = <&dvfs_opp_table>;

        interconnects = <&mc TEGRA30_MC_MPCORER &emc>;

        interconnect-names = "cpu-read";

        #cooling-cells = <2>;

    };

drivers/devfreq/Kconfig

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@@ -103,7 +103,6 @@ config ARM_IMX8M_DDRC_DEVFREQ 
	tristate "i.MX8M DDRC DEVFREQ Driver"

	depends on (ARCH_MXC && HAVE_ARM_SMCCC) || \

		(COMPILE_TEST && HAVE_ARM_SMCCC)

	select DEVFREQ_GOV_SIMPLE_ONDEMAND

	select DEVFREQ_GOV_USERSPACE

	help

	  This adds the DEVFREQ driver for the i.MX8M DDR Controller. It allows

drivers/devfreq/devfreq.c

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@@ -823,6 +823,7 @@ struct devfreq *devfreq_add_device(struct device *dev, 
	if (devfreq->profile->timer < 0

		|| devfreq->profile->timer >= DEVFREQ_TIMER_NUM) {

		mutex_unlock(&devfreq->lock);

		err = -EINVAL;

		goto err_dev;

	}

drivers/devfreq/governor_passive.c

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@@ -65,7 +65,7 @@ static int devfreq_passive_get_target_freq(struct devfreq *devfreq, 
		dev_pm_opp_put(p_opp);



		if (IS_ERR(opp))

			return PTR_ERR(opp);

			goto no_required_opp;



		*freq = dev_pm_opp_get_freq(opp);

		dev_pm_opp_put(opp);
@@ -73,6 +73,7 @@ static int devfreq_passive_get_target_freq(struct devfreq *devfreq, 
		return 0;

	}



no_required_opp:

	/*

	 * Get the OPP table's index of decided frequency by governor

	 * of parent device.