Unverified Commit bc47b221 authored by Conor Dooley's avatar Conor Dooley Committed by Palmer Dabbelt
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riscv: dts: microchip: add the sundance polarberry 



Add a minimal device tree for the PolarFire SoC based Sundance
PolarBerry.

Reviewed-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220509142610.128590-9-conor.dooley@microchip.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent b847d32a

arch/riscv/boot/dts/microchip/Makefile

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# SPDX-License-Identifier: GPL-2.0

dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb

dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb

obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)

/* Copyright (c) 2020-2022 Microchip Technology Inc */



/ {

	fabric_clk3: fabric-clk3 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <62500000>;

	};



	fabric_clk1: fabric-clk1 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <125000000>;

	};

};

arch/riscv/boot/dts/microchip/mpfs-polarberry.dts

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)

/* Copyright (c) 2020-2022 Microchip Technology Inc */



/dts-v1/;



#include "mpfs.dtsi"

#include "mpfs-polarberry-fabric.dtsi"



/* Clock frequency (in Hz) of the rtcclk */

#define MTIMER_FREQ	1000000



/ {

	model = "Sundance PolarBerry";

	compatible = "sundance,polarberry", "microchip,mpfs";



	aliases {

		ethernet0 = &mac1;

		serial0 = &mmuart0;

	};



	chosen {

		stdout-path = "serial0:115200n8";

	};



	cpus {

		timebase-frequency = <MTIMER_FREQ>;

	};



	ddrc_cache_lo: memory@80000000 {

		device_type = "memory";

		reg = <0x0 0x80000000 0x0 0x2e000000>;

	};



	ddrc_cache_hi: memory@1000000000 {

		device_type = "memory";

		reg = <0x10 0x00000000 0x0 0xC0000000>;

	};

};



/*

 * phy0 is connected to mac0, but the port itself is on the (optional) carrier

 * board.

 */

&mac0 {

	phy-mode = "sgmii";

	phy-handle = <&phy0>;

	status = "disabled";

};



&mac1 {

	phy-mode = "sgmii";

	phy-handle = <&phy1>;

	status = "okay";



	phy1: ethernet-phy@5 {

		reg = <5>;

		ti,fifo-depth = <0x01>;

	};



	phy0: ethernet-phy@4 {

		reg = <4>;

		ti,fifo-depth = <0x01>;

	};

};



&mbox {

	status = "okay";

};



&mmc {

	bus-width = <4>;

	disable-wp;

	cap-sd-highspeed;

	cap-mmc-highspeed;

	card-detect-delay = <200>;

	mmc-ddr-1_8v;

	mmc-hs200-1_8v;

	sd-uhs-sdr12;

	sd-uhs-sdr25;

	sd-uhs-sdr50;

	sd-uhs-sdr104;

	status = "okay";

};



&mmuart0 {

	status = "okay";

};



&refclk {

	clock-frequency = <125000000>;

};



&rtc {

	status = "okay";

};



&syscontroller {

	status = "okay";

};