Commit bc45f524 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch '1GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue 



Tony Nguyen says:

====================
1GbE Intel Wired LAN Driver Updates 2021-04-16

This series contains updates to igb and igc drivers.

Ederson adjusts Tx buffer distributions in Qav mode to improve
TSN-aware traffic for igb. He also enable PPS support and auxiliary PHC
functions for igc.

Grzegorz checks that the MTA register was properly written and
retries if not for igb.

Sasha adds reporting of EEE low power idle counters to ethtool and fixes
a return value being overwritten through looping for igc.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 1e3d976d 1feaf60f

drivers/net/ethernet/intel/igb/e1000_defines.h

+4 −4
Original line number Diff line number Diff line
@@ -340,10 +340,10 @@ 
#define I210_RXPBSIZE_PB_32KB		0x00000020

#define I210_TXPBSIZE_DEFAULT		0x04000014 /* TXPBSIZE default */

#define I210_TXPBSIZE_MASK		0xC0FFFFFF

#define I210_TXPBSIZE_PB0_8KB		(8 << 0)

#define I210_TXPBSIZE_PB1_8KB		(8 << 6)

#define I210_TXPBSIZE_PB2_4KB		(4 << 12)

#define I210_TXPBSIZE_PB3_4KB		(4 << 18)

#define I210_TXPBSIZE_PB0_6KB		(6 << 0)

#define I210_TXPBSIZE_PB1_6KB		(6 << 6)

#define I210_TXPBSIZE_PB2_6KB		(6 << 12)

#define I210_TXPBSIZE_PB3_6KB		(6 << 18)



#define I210_DTXMXPKTSZ_DEFAULT		0x00000098

drivers/net/ethernet/intel/igb/e1000_mac.c

+27 −0
Original line number Diff line number Diff line
@@ -483,6 +483,31 @@ static u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) 
	return hash_value;

}



/**

 * igb_i21x_hw_doublecheck - double checks potential HW issue in i21X

 * @hw: pointer to the HW structure

 *

 * Checks if multicast array is wrote correctly

 * If not then rewrites again to register

 **/

static void igb_i21x_hw_doublecheck(struct e1000_hw *hw)

{

	bool is_failed;

	int i;



	do {

		is_failed = false;

		for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) {

			if (array_rd32(E1000_MTA, i) != hw->mac.mta_shadow[i]) {

				is_failed = true;

				array_wr32(E1000_MTA, i, hw->mac.mta_shadow[i]);

				wrfl();

				break;

			}

		}

	} while (is_failed);

}



/**

 *  igb_update_mc_addr_list - Update Multicast addresses

 *  @hw: pointer to the HW structure
@@ -516,6 +541,8 @@ void igb_update_mc_addr_list(struct e1000_hw *hw, 
	for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)

		array_wr32(E1000_MTA, i, hw->mac.mta_shadow[i]);

	wrfl();

	if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211)

		igb_i21x_hw_doublecheck(hw);

}



/**

drivers/net/ethernet/intel/igb/igb_main.c

+2 −2
Original line number Diff line number Diff line
@@ -1921,8 +1921,8 @@ static void igb_setup_tx_mode(struct igb_adapter *adapter) 
		 */

		val = rd32(E1000_TXPBS);

		val &= ~I210_TXPBSIZE_MASK;

		val |= I210_TXPBSIZE_PB0_8KB | I210_TXPBSIZE_PB1_8KB |

			I210_TXPBSIZE_PB2_4KB | I210_TXPBSIZE_PB3_4KB;

		val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB |

			I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB;

		wr32(E1000_TXPBS, val);



		val = rd32(E1000_RXPBS);

drivers/net/ethernet/intel/igc/igc.h

+13 −0
Original line number Diff line number Diff line
@@ -28,6 +28,11 @@ void igc_ethtool_set_ops(struct net_device *); 
#define MAX_ETYPE_FILTER		8

#define IGC_RETA_SIZE			128



/* SDP support */

#define IGC_N_EXTTS	2

#define IGC_N_PEROUT	2

#define IGC_N_SDP	4



enum igc_mac_filter_type {

	IGC_MAC_FILTER_TYPE_DST = 0,

	IGC_MAC_FILTER_TYPE_SRC
@@ -223,6 +228,14 @@ struct igc_adapter { 
	char fw_version[32];



	struct bpf_prog *xdp_prog;



	bool pps_sys_wrap_on;



	struct ptp_pin_desc sdp_config[IGC_N_SDP];

	struct {

		struct timespec64 start;

		struct timespec64 period;

	} perout[IGC_N_PEROUT];

};



void igc_up(struct igc_adapter *adapter);

drivers/net/ethernet/intel/igc/igc_defines.h

+63 −0
Original line number Diff line number Diff line
@@ -8,6 +8,8 @@ 
#define REQ_TX_DESCRIPTOR_MULTIPLE	8

#define REQ_RX_DESCRIPTOR_MULTIPLE	8



#define IGC_CTRL_EXT_SDP2_DIR	0x00000400 /* SDP2 Data direction */

#define IGC_CTRL_EXT_SDP3_DIR	0x00000800 /* SDP3 Data direction */

#define IGC_CTRL_EXT_DRV_LOAD	0x10000000 /* Drv loaded bit for FW */



/* Definitions for power management and wakeup registers */
@@ -96,6 +98,9 @@ 
#define IGC_CTRL_RFCE		0x08000000  /* Receive Flow Control enable */

#define IGC_CTRL_TFCE		0x10000000  /* Transmit flow control enable */



#define IGC_CTRL_SDP0_DIR 0x00400000	/* SDP0 Data direction */

#define IGC_CTRL_SDP1_DIR 0x00800000	/* SDP1 Data direction */



/* As per the EAS the maximum supported size is 9.5KB (9728 bytes) */

#define MAX_JUMBO_FRAME_SIZE	0x2600
@@ -403,6 +408,64 @@ 
#define IGC_TSYNCTXCTL_START_SYNC		0x80000000  /* initiate sync */

#define IGC_TSYNCTXCTL_TXSYNSIG			0x00000020  /* Sample TX tstamp in PHY sop */



/* Timer selection bits */

#define IGC_AUX_IO_TIMER_SEL_SYSTIM0	(0u << 30) /* Select SYSTIM0 for auxiliary time stamp */

#define IGC_AUX_IO_TIMER_SEL_SYSTIM1	(1u << 30) /* Select SYSTIM1 for auxiliary time stamp */

#define IGC_AUX_IO_TIMER_SEL_SYSTIM2	(2u << 30) /* Select SYSTIM2 for auxiliary time stamp */

#define IGC_AUX_IO_TIMER_SEL_SYSTIM3	(3u << 30) /* Select SYSTIM3 for auxiliary time stamp */

#define IGC_TT_IO_TIMER_SEL_SYSTIM0	(0u << 30) /* Select SYSTIM0 for target time stamp */

#define IGC_TT_IO_TIMER_SEL_SYSTIM1	(1u << 30) /* Select SYSTIM1 for target time stamp */

#define IGC_TT_IO_TIMER_SEL_SYSTIM2	(2u << 30) /* Select SYSTIM2 for target time stamp */

#define IGC_TT_IO_TIMER_SEL_SYSTIM3	(3u << 30) /* Select SYSTIM3 for target time stamp */



/* TSAUXC Configuration Bits */

#define IGC_TSAUXC_EN_TT0	BIT(0)  /* Enable target time 0. */

#define IGC_TSAUXC_EN_TT1	BIT(1)  /* Enable target time 1. */

#define IGC_TSAUXC_EN_CLK0	BIT(2)  /* Enable Configurable Frequency Clock 0. */

#define IGC_TSAUXC_EN_CLK1	BIT(5)  /* Enable Configurable Frequency Clock 1. */

#define IGC_TSAUXC_EN_TS0	BIT(8)  /* Enable hardware timestamp 0. */

#define IGC_TSAUXC_AUTT0	BIT(9)  /* Auxiliary Timestamp Taken. */

#define IGC_TSAUXC_EN_TS1	BIT(10) /* Enable hardware timestamp 0. */

#define IGC_TSAUXC_AUTT1	BIT(11) /* Auxiliary Timestamp Taken. */

#define IGC_TSAUXC_PLSG		BIT(17) /* Generate a pulse. */

#define IGC_TSAUXC_DISABLE1	BIT(27) /* Disable SYSTIM0 Count Operation. */

#define IGC_TSAUXC_DISABLE2	BIT(28) /* Disable SYSTIM1 Count Operation. */

#define IGC_TSAUXC_DISABLE3	BIT(29) /* Disable SYSTIM2 Count Operation. */

#define IGC_TSAUXC_DIS_TS_CLEAR	BIT(30) /* Disable EN_TT0/1 auto clear. */

#define IGC_TSAUXC_DISABLE0	BIT(31) /* Disable SYSTIM0 Count Operation. */



/* SDP Configuration Bits */

#define IGC_AUX0_SEL_SDP0	(0u << 0)  /* Assign SDP0 to auxiliary time stamp 0. */

#define IGC_AUX0_SEL_SDP1	(1u << 0)  /* Assign SDP1 to auxiliary time stamp 0. */

#define IGC_AUX0_SEL_SDP2	(2u << 0)  /* Assign SDP2 to auxiliary time stamp 0. */

#define IGC_AUX0_SEL_SDP3	(3u << 0)  /* Assign SDP3 to auxiliary time stamp 0. */

#define IGC_AUX0_TS_SDP_EN	(1u << 2)  /* Enable auxiliary time stamp trigger 0. */

#define IGC_AUX1_SEL_SDP0	(0u << 3)  /* Assign SDP0 to auxiliary time stamp 1. */

#define IGC_AUX1_SEL_SDP1	(1u << 3)  /* Assign SDP1 to auxiliary time stamp 1. */

#define IGC_AUX1_SEL_SDP2	(2u << 3)  /* Assign SDP2 to auxiliary time stamp 1. */

#define IGC_AUX1_SEL_SDP3	(3u << 3)  /* Assign SDP3 to auxiliary time stamp 1. */

#define IGC_AUX1_TS_SDP_EN	(1u << 5)  /* Enable auxiliary time stamp trigger 1. */

#define IGC_TS_SDP0_SEL_TT0	(0u << 6)  /* Target time 0 is output on SDP0. */

#define IGC_TS_SDP0_SEL_TT1	(1u << 6)  /* Target time 1 is output on SDP0. */

#define IGC_TS_SDP0_SEL_FC0	(2u << 6)  /* Freq clock  0 is output on SDP0. */

#define IGC_TS_SDP0_SEL_FC1	(3u << 6)  /* Freq clock  1 is output on SDP0. */

#define IGC_TS_SDP0_EN		(1u << 8)  /* SDP0 is assigned to Tsync. */

#define IGC_TS_SDP1_SEL_TT0	(0u << 9)  /* Target time 0 is output on SDP1. */

#define IGC_TS_SDP1_SEL_TT1	(1u << 9)  /* Target time 1 is output on SDP1. */

#define IGC_TS_SDP1_SEL_FC0	(2u << 9)  /* Freq clock  0 is output on SDP1. */

#define IGC_TS_SDP1_SEL_FC1	(3u << 9)  /* Freq clock  1 is output on SDP1. */

#define IGC_TS_SDP1_EN		(1u << 11) /* SDP1 is assigned to Tsync. */

#define IGC_TS_SDP2_SEL_TT0	(0u << 12) /* Target time 0 is output on SDP2. */

#define IGC_TS_SDP2_SEL_TT1	(1u << 12) /* Target time 1 is output on SDP2. */

#define IGC_TS_SDP2_SEL_FC0	(2u << 12) /* Freq clock  0 is output on SDP2. */

#define IGC_TS_SDP2_SEL_FC1	(3u << 12) /* Freq clock  1 is output on SDP2. */

#define IGC_TS_SDP2_EN		(1u << 14) /* SDP2 is assigned to Tsync. */

#define IGC_TS_SDP3_SEL_TT0	(0u << 15) /* Target time 0 is output on SDP3. */

#define IGC_TS_SDP3_SEL_TT1	(1u << 15) /* Target time 1 is output on SDP3. */

#define IGC_TS_SDP3_SEL_FC0	(2u << 15) /* Freq clock  0 is output on SDP3. */

#define IGC_TS_SDP3_SEL_FC1	(3u << 15) /* Freq clock  1 is output on SDP3. */

#define IGC_TS_SDP3_EN		(1u << 17) /* SDP3 is assigned to Tsync. */



/* Transmit Scheduling */

#define IGC_TQAVCTRL_TRANSMIT_MODE_TSN	0x00000001

#define IGC_TQAVCTRL_ENHANCED_QAV	0x00000008