Commit bc3fc5c0 authored by Fabien Parent's avatar Fabien Parent Committed by Matthias Brugger
Browse files

soc: mediatek: mmsys: add MT8365 support 



Add DSI mmsys connections for the MT8365 SoC.

Signed-off-by: default avatarFabien Parent <fparent@baylibre.com>
Link: https://lore.kernel.org/r/20210519161847.3747352-3-fparent@baylibre.com


[mb: take the mask field into account]
Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 7bdcead7

drivers/soc/mediatek/mt8365-mmsys.h

0 → 100644
+60 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */



#ifndef __SOC_MEDIATEK_MT8365_MMSYS_H

#define __SOC_MEDIATEK_MT8365_MMSYS_H



#define MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0xf3c

#define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL	0xf4c

#define MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN	0xf50

#define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN	0xf54

#define MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN	0xf60

#define MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0xf64

#define MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN		0xf68



#define MT8365_RDMA0_SOUT_COLOR0			0x1

#define MT8365_DITHER_MOUT_EN_DSI0			0x1

#define MT8365_DSI0_SEL_IN_DITHER			0x1

#define MT8365_RDMA0_SEL_IN_OVL0			0x0

#define MT8365_RDMA0_RSZ0_SEL_IN_RDMA0			0x0

#define MT8365_DISP_COLOR_SEL_IN_COLOR0			0x0

#define MT8365_OVL0_MOUT_PATH0_SEL			BIT(0)



static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {

	{

		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,

		MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,

		MT8365_OVL0_MOUT_PATH0_SEL, MT8365_OVL0_MOUT_PATH0_SEL

	},

	{

		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,

		MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN,

		MT8365_RDMA0_SEL_IN_OVL0, MT8365_RDMA0_SEL_IN_OVL0

	},

	{

		DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,

		MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL,

		MT8365_RDMA0_SOUT_COLOR0, MT8365_RDMA0_SOUT_COLOR0

	},

	{

		DDP_COMPONENT_COLOR0, DDP_COMPONENT_CCORR,

		MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,

		MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0

	},

	{

		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,

		MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,

		MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0

	},

	{

		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,

		MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,

		MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER

	},

	{

		DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,

		MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN,

		MT8365_RDMA0_RSZ0_SEL_IN_RDMA0, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0

	},

};



#endif /* __SOC_MEDIATEK_MT8365_MMSYS_H */

drivers/soc/mediatek/mtk-mmsys.c

+11 −0
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include "mtk-mmsys.h"

#include "mt8167-mmsys.h"

#include "mt8183-mmsys.h"

#include "mt8365-mmsys.h"



static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {

	.clk_driver = "clk-mt2701-mm",
@@ -52,6 +53,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { 
	.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),

};



static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {

	.clk_driver = "clk-mt8365-mm",

	.routes = mt8365_mmsys_routing_table,

	.num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),

};



struct mtk_mmsys {

	void __iomem *regs;

	const struct mtk_mmsys_driver_data *data;
@@ -160,6 +167,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = { 
		.compatible = "mediatek,mt8183-mmsys",

		.data = &mt8183_mmsys_driver_data,

	},

	{

		.compatible = "mediatek,mt8365-mmsys",

		.data = &mt8365_mmsys_driver_data,

	},

	{ }

};