Commit bc143d8b authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/pm: do not expose implementation details to other blocks out of power 



Those implementation details(whether swsmu supported, some ppt_funcs supported,
accessing internal statistics ...)should be kept internally. It's not a good
practice and even error prone to expose implementation details.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8c2d34eb

drivers/gpu/drm/amd/amdgpu/aldebaran.c

+1 −1
Original line number Diff line number Diff line
@@ -260,7 +260,7 @@ static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev) 
	adev->gfx.rlc.funcs->resume(adev);



	/* Wait for FW reset event complete */

	r = smu_wait_for_event(adev, SMU_EVENT_RESET_COMPLETE, 0);

	r = amdgpu_dpm_wait_for_event(adev, SMU_EVENT_RESET_COMPLETE, 0);

	if (r) {

		dev_err(adev->dev,

			"Failed to get response from firmware after reset\n");

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

+14 −11
Original line number Diff line number Diff line
@@ -1585,22 +1585,25 @@ static int amdgpu_debugfs_sclk_set(void *data, u64 val) 
		return ret;

	}



	if (is_support_sw_smu(adev)) {

		ret = smu_get_dpm_freq_range(&adev->smu, SMU_SCLK, &min_freq, &max_freq);

		if (ret || val > max_freq || val < min_freq)

			return -EINVAL;

		ret = smu_set_soft_freq_range(&adev->smu, SMU_SCLK, (uint32_t)val, (uint32_t)val);

	} else {

		return 0;

	ret = amdgpu_dpm_get_dpm_freq_range(adev, PP_SCLK, &min_freq, &max_freq);

	if (ret == -EOPNOTSUPP) {

		ret = 0;

		goto out;

	}

	if (ret || val > max_freq || val < min_freq) {

		ret = -EINVAL;

		goto out;

	}



	ret = amdgpu_dpm_set_soft_freq_range(adev, PP_SCLK, (uint32_t)val, (uint32_t)val);

	if (ret)

		ret = -EINVAL;



out:

	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);

	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);



	if (ret)

		return -EINVAL;



	return 0;

	return ret;

}



DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL,

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+3 −3
Original line number Diff line number Diff line
@@ -2624,7 +2624,7 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) 
	/* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */

	if (amdgpu_passthrough(adev) && ((adev->asic_type == CHIP_ARCTURUS && adev->gmc.xgmi.num_physical_nodes > 1)||

			       adev->asic_type == CHIP_ALDEBARAN ))

		smu_handle_passthrough_sbr(&adev->smu, true);

		amdgpu_dpm_handle_passthrough_sbr(adev, true);



	if (adev->gmc.xgmi.num_physical_nodes > 1) {

		mutex_lock(&mgpu_info.mutex);
@@ -2881,7 +2881,7 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) 
	int i, r;



	if (adev->in_s0ix)

		amdgpu_gfx_state_change_set(adev, sGpuChangeState_D3Entry);

		amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D3Entry);



	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {

		if (!adev->ip_blocks[i].status.valid)
@@ -4044,7 +4044,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon) 
		return 0;



	if (adev->in_s0ix)

		amdgpu_gfx_state_change_set(adev, sGpuChangeState_D0Entry);

		amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D0Entry);



	/* post card */

	if (amdgpu_device_need_post(adev)) {

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

+1 −17
Original line number Diff line number Diff line
@@ -615,7 +615,7 @@ int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value) 


	mutex_lock(&adev->gfx.gfx_off_mutex);



	r = smu_get_status_gfxoff(adev, value);

	r = amdgpu_dpm_get_status_gfxoff(adev, value);



	mutex_unlock(&adev->gfx.gfx_off_mutex);
@@ -852,19 +852,3 @@ int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev) 
	}

	return amdgpu_num_kcq;

}
 


/* amdgpu_gfx_state_change_set - Handle gfx power state change set

 * @adev: amdgpu_device pointer

 * @state: gfx power state(1 -sGpuChangeState_D0Entry and 2 -sGpuChangeState_D3Entry)

 *

 */



void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum gfx_change_state state)

{

	mutex_lock(&adev->pm.mutex);

	if (adev->powerplay.pp_funcs &&

	    adev->powerplay.pp_funcs->gfx_state_change_set)

		((adev)->powerplay.pp_funcs->gfx_state_change_set(

			(adev)->powerplay.pp_handle, state));

	mutex_unlock(&adev->pm.mutex);

}

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

+0 −7
Original line number Diff line number Diff line
@@ -47,12 +47,6 @@ enum amdgpu_gfx_pipe_priority { 
	AMDGPU_GFX_PIPE_PRIO_HIGH = AMDGPU_RING_PRIO_2

};



/* Argument for PPSMC_MSG_GpuChangeState */

enum gfx_change_state {

	sGpuChangeState_D0Entry = 1,

	sGpuChangeState_D3Entry,

};



#define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM  0

#define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM  15
@@ -410,5 +404,4 @@ int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, 
uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);

void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);

int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);

void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum gfx_change_state state);

#endif