Commit bbc78013 authored by Vladimir Zapolskiy's avatar Vladimir Zapolskiy Committed by Bjorn Andersson
Browse files

clk: qcom: clk-alpha-pll: add Rivian EVO PLL configuration interfaces 



Add and export Rivian EVO PLL configuration and control functions to
clock controller drivers, the PLL is used by SM8450 camera clock
controller.

Reviewed-by: default avatarStephen Boyd <sboyd@kernel.org>
Reviewed-by: default avatarVinod Koul <vkoul@kernel.org>
Signed-off-by: default avatarVladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220701062739.2757912-1-vladimir.zapolskiy@linaro.org
parent 260e3660

drivers/clk/qcom/clk-alpha-pll.c

+70 −0
Original line number Diff line number Diff line
@@ -154,6 +154,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 
		[PLL_OFF_TEST_CTL_U] = 0x30,

		[PLL_OFF_TEST_CTL_U1] = 0x34,

	},

	[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = {

		[PLL_OFF_OPMODE] = 0x04,

		[PLL_OFF_STATUS] = 0x0c,

		[PLL_OFF_L_VAL] = 0x10,

		[PLL_OFF_USER_CTL] = 0x14,

		[PLL_OFF_USER_CTL_U] = 0x18,

		[PLL_OFF_CONFIG_CTL] = 0x1c,

		[PLL_OFF_CONFIG_CTL_U] = 0x20,

		[PLL_OFF_CONFIG_CTL_U1] = 0x24,

		[PLL_OFF_TEST_CTL] = 0x28,

		[PLL_OFF_TEST_CTL_U] = 0x2c,

	},

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
@@ -2178,3 +2190,61 @@ const struct clk_ops clk_alpha_pll_lucid_evo_ops = { 
	.set_rate = alpha_pll_lucid_5lpe_set_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops);



void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

				  const struct alpha_pll_config *config)

{

	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);

	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);

	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);

	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);

	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);

	clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);

	clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);

	clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);



	regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);



	regmap_update_bits(regmap, PLL_MODE(pll),

			   PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL,

			   PLL_RESET_N | PLL_BYPASSNL);

}

EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure);



static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw,

						    unsigned long parent_rate)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	u32 l;



	regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);



	return parent_rate * l;

}



static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate,

					  unsigned long *prate)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	unsigned long min_freq, max_freq;

	u32 l;

	u64 a;



	rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0);

	if (!pll->vco_table || alpha_pll_find_vco(pll, rate))

		return rate;



	min_freq = pll->vco_table[0].min_freq;

	max_freq = pll->vco_table[pll->num_vco - 1].max_freq;



	return clamp(rate, min_freq, max_freq);

}



const struct clk_ops clk_alpha_pll_rivian_evo_ops = {

	.enable = alpha_pll_lucid_5lpe_enable,

	.disable = alpha_pll_lucid_5lpe_disable,

	.is_enabled = clk_trion_pll_is_enabled,

	.recalc_rate = clk_rivian_evo_pll_recalc_rate,

	.round_rate = clk_rivian_evo_pll_round_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops);

drivers/clk/qcom/clk-alpha-pll.h

+6 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ enum { 
	CLK_ALPHA_PLL_TYPE_AGERA,

	CLK_ALPHA_PLL_TYPE_ZONDA,

	CLK_ALPHA_PLL_TYPE_LUCID_EVO,

	CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,

	CLK_ALPHA_PLL_TYPE_MAX,

};
@@ -157,6 +158,9 @@ extern const struct clk_ops clk_alpha_pll_lucid_evo_ops; 
extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;

extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;



extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;

#define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops



void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

			     const struct alpha_pll_config *config);

void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
@@ -172,5 +176,7 @@ void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 
			     const struct alpha_pll_config *config);

void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

				 const struct alpha_pll_config *config);

void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

				  const struct alpha_pll_config *config);



#endif