Commit bbc42ab0 authored by Emil Velikov's avatar Emil Velikov Committed by Mauro Carvalho Chehab
Browse files

media: hantro: introduce hantro_g1.c for common API 



The Hantro G1 IRQ and reset handling is pretty standard. I was this
close to duplicating it, yet again, before reconsidering and refactoring
it to a separate file.

Acked-by: default avatarNicolas Ferre <nicolas.ferre@microchip.com>
Reviewed-by: default avatarEzequiel Garcia <ezequiel@collabora.com>
Reviewed-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: default avatarEmil Velikov <emil.velikov@collabora.com>
Signed-off-by: default avatarHans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
parent d72a96b6

drivers/staging/media/hantro/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ hantro-vpu-y += \ 
		hantro_v4l2.o \

		hantro_postproc.o \

		hantro_h1_jpeg_enc.o \

		hantro_g1.o \

		hantro_g1_h264_dec.o \

		hantro_g1_mpeg2_dec.o \

		hantro_g1_vp8_dec.o \

drivers/staging/media/hantro/hantro_g1.c

0 → 100644
+39 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Hantro VPU codec driver

 *

 * Copyright (C) 2018 Rockchip Electronics Co., Ltd.

 *	Jeffy Chen <jeffy.chen@rock-chips.com>

 * Copyright (C) 2019 Pengutronix, Philipp Zabel <kernel@pengutronix.de>

 * Copyright (C) 2021 Collabora Ltd, Emil Velikov <emil.velikov@collabora.com>

 */



#include "hantro.h"

#include "hantro_g1_regs.h"



irqreturn_t hantro_g1_irq(int irq, void *dev_id)

{

	struct hantro_dev *vpu = dev_id;

	enum vb2_buffer_state state;

	u32 status;



	status = vdpu_read(vpu, G1_REG_INTERRUPT);

	state = (status & G1_REG_INTERRUPT_DEC_RDY_INT) ?

		 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;



	vdpu_write(vpu, 0, G1_REG_INTERRUPT);

	vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);



	hantro_irq_done(vpu, state);



	return IRQ_HANDLED;

}



void hantro_g1_reset(struct hantro_ctx *ctx)

{

	struct hantro_dev *vpu = ctx->dev;



	vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT);

	vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);

	vdpu_write(vpu, 1, G1_REG_SOFT_RESET);

}

drivers/staging/media/hantro/hantro_hw.h

+3 −0
Original line number Diff line number Diff line
@@ -176,6 +176,9 @@ void hantro_irq_done(struct hantro_dev *vpu, 
void hantro_start_prepare_run(struct hantro_ctx *ctx);

void hantro_end_prepare_run(struct hantro_ctx *ctx);



irqreturn_t hantro_g1_irq(int irq, void *dev_id);

void hantro_g1_reset(struct hantro_ctx *ctx);



void hantro_h1_jpeg_enc_run(struct hantro_ctx *ctx);

void rk3399_vpu_jpeg_enc_run(struct hantro_ctx *ctx);

int hantro_jpeg_enc_init(struct hantro_ctx *ctx);

drivers/staging/media/hantro/imx8m_vpu_hw.c

+1 −20
Original line number Diff line number Diff line
@@ -9,7 +9,6 @@ 
#include <linux/delay.h>



#include "hantro.h"

#include "hantro_g1_regs.h"



#define CTRL_SOFT_RESET		0x00

#define RESET_G1		BIT(1)
@@ -129,24 +128,6 @@ static const struct hantro_fmt imx8m_vpu_dec_fmts[] = { 
	},

};



static irqreturn_t imx8m_vpu_g1_irq(int irq, void *dev_id)

{

	struct hantro_dev *vpu = dev_id;

	enum vb2_buffer_state state;

	u32 status;



	status = vdpu_read(vpu, G1_REG_INTERRUPT);

	state = (status & G1_REG_INTERRUPT_DEC_RDY_INT) ?

		 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;



	vdpu_write(vpu, 0, G1_REG_INTERRUPT);

	vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);



	hantro_irq_done(vpu, state);



	return IRQ_HANDLED;

}



static int imx8mq_vpu_hw_init(struct hantro_dev *vpu)

{

	vpu->ctrl_base = vpu->reg_bases[vpu->variant->num_regs - 1];
@@ -191,7 +172,7 @@ static const struct hantro_codec_ops imx8mq_vpu_codec_ops[] = { 
 */



static const struct hantro_irq imx8mq_irqs[] = {

	{ "g1", imx8m_vpu_g1_irq },

	{ "g1", hantro_g1_irq },

	{ "g2", NULL /* TODO: imx8m_vpu_g2_irq */ },

};

drivers/staging/media/hantro/rk3288_vpu_hw.c

+4 −32
Original line number Diff line number Diff line
@@ -10,7 +10,6 @@ 


#include "hantro.h"

#include "hantro_jpeg.h"

#include "hantro_g1_regs.h"

#include "hantro_h1_regs.h"



#define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000)
@@ -127,24 +126,6 @@ static irqreturn_t rk3288_vepu_irq(int irq, void *dev_id) 
	return IRQ_HANDLED;

}



static irqreturn_t rk3288_vdpu_irq(int irq, void *dev_id)

{

	struct hantro_dev *vpu = dev_id;

	enum vb2_buffer_state state;

	u32 status;



	status = vdpu_read(vpu, G1_REG_INTERRUPT);

	state = (status & G1_REG_INTERRUPT_DEC_RDY_INT) ?

		VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;



	vdpu_write(vpu, 0, G1_REG_INTERRUPT);

	vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);



	hantro_irq_done(vpu, state);



	return IRQ_HANDLED;

}



static int rk3288_vpu_hw_init(struct hantro_dev *vpu)

{

	/* Bump ACLK to max. possible freq. to improve performance. */
@@ -161,15 +142,6 @@ static void rk3288_vpu_enc_reset(struct hantro_ctx *ctx) 
	vepu_write(vpu, 0, H1_REG_AXI_CTRL);

}



static void rk3288_vpu_dec_reset(struct hantro_ctx *ctx)

{

	struct hantro_dev *vpu = ctx->dev;



	vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT);

	vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);

	vdpu_write(vpu, 1, G1_REG_SOFT_RESET);

}



/*

 * Supported codec ops.

 */
@@ -184,19 +156,19 @@ static const struct hantro_codec_ops rk3288_vpu_codec_ops[] = { 
	},

	[HANTRO_MODE_H264_DEC] = {

		.run = hantro_g1_h264_dec_run,

		.reset = rk3288_vpu_dec_reset,

		.reset = hantro_g1_reset,

		.init = hantro_h264_dec_init,

		.exit = hantro_h264_dec_exit,

	},

	[HANTRO_MODE_MPEG2_DEC] = {

		.run = hantro_g1_mpeg2_dec_run,

		.reset = rk3288_vpu_dec_reset,

		.reset = hantro_g1_reset,

		.init = hantro_mpeg2_dec_init,

		.exit = hantro_mpeg2_dec_exit,

	},

	[HANTRO_MODE_VP8_DEC] = {

		.run = hantro_g1_vp8_dec_run,

		.reset = rk3288_vpu_dec_reset,

		.reset = hantro_g1_reset,

		.init = hantro_vp8_dec_init,

		.exit = hantro_vp8_dec_exit,

	},
@@ -208,7 +180,7 @@ static const struct hantro_codec_ops rk3288_vpu_codec_ops[] = { 


static const struct hantro_irq rk3288_irqs[] = {

	{ "vepu", rk3288_vepu_irq },

	{ "vdpu", rk3288_vdpu_irq },

	{ "vdpu", hantro_g1_irq },

};



static const char * const rk3288_clk_names[] = {