Commit bbab3110 authored by Gayatri Kammela's avatar Gayatri Kammela Committed by Hans de Goede
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platform/x86/intel: pmc/core: Add Alderlake support to pmc core driver 



Add Alder Lake client and mobile support to pmc core driver.

Cc: Chao Qin <chao.qin@intel.com>
Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: David Box <david.e.box@intel.com>
Tested-by: default avatarYou-Sheng Yang <vicamo.yang@canonical.com>
Acked-by: default avatarRajneesh Bhardwaj <irenic.rajneesh@gmail.com>
Reviewed-by: default avatarHans de Goede <hdegoede@redhat.com>
Reviewed-by: default avatarAndy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: default avatarGayatri Kammela <gayatri.kammela@intel.com>
Link: https://lore.kernel.org/r/8b32e168f8e69dd00aabfb2e4383db78f22b123b.1629091915.git.gayatri.kammela@intel.com


Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
parent 95c3e4b4

drivers/platform/x86/intel/pmc/core.c

+68 −0
Original line number Diff line number Diff line
@@ -645,6 +645,73 @@ static void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev) 
	ACPI_FREE(out_obj);

}



/* Alder Lake: PGD PFET Enable Ack Status Register(s) bitmap */

static const struct pmc_bit_map adl_pfear_map[] = {

	{"SPI/eSPI",		BIT(2)},

	{"XHCI",		BIT(3)},

	{"SPA",			BIT(4)},

	{"SPB",			BIT(5)},

	{"SPC",			BIT(6)},

	{"GBE",			BIT(7)},



	{"SATA",		BIT(0)},

	{"HDA_PGD0",		BIT(1)},

	{"HDA_PGD1",		BIT(2)},

	{"HDA_PGD2",		BIT(3)},

	{"HDA_PGD3",		BIT(4)},

	{"SPD",			BIT(5)},

	{"LPSS",		BIT(6)},



	{"SMB",			BIT(0)},

	{"ISH",			BIT(1)},

	{"ITH",			BIT(3)},



	{"XDCI",		BIT(1)},

	{"DCI",			BIT(2)},

	{"CSE",			BIT(3)},

	{"CSME_KVM",		BIT(4)},

	{"CSME_PMT",		BIT(5)},

	{"CSME_CLINK",		BIT(6)},

	{"CSME_PTIO",		BIT(7)},



	{"CSME_USBR",		BIT(0)},

	{"CSME_SUSRAM",		BIT(1)},

	{"CSME_SMT1",		BIT(2)},

	{"CSME_SMS2",		BIT(4)},

	{"CSME_SMS1",		BIT(5)},

	{"CSME_RTC",		BIT(6)},

	{"CSME_PSF",		BIT(7)},



	{"CNVI",		BIT(3)},



	{"HDA_PGD4",		BIT(2)},

	{"HDA_PGD5",		BIT(3)},

	{"HDA_PGD6",		BIT(4)},

	{}

};



static const struct pmc_bit_map *ext_adl_pfear_map[] = {

	/*

	 * Check intel_pmc_core_ids[] users of cnp_reg_map for

	 * a list of core SoCs using this.

	 */

	adl_pfear_map,

	NULL

};



static const struct pmc_reg_map adl_reg_map = {

	.pfear_sts = ext_adl_pfear_map,

	.slp_s0_offset = ADL_PMC_SLP_S0_RES_COUNTER_OFFSET,

	.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,

	.msr_sts = msr_map,

	.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,

	.regmap_length = CNP_PMC_MMIO_REG_LEN,

	.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,

	.ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,

	.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,

	.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,

};



static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)

{

	return readl(pmcdev->regbase + reg_offset);
@@ -1611,6 +1678,7 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = { 
	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L,	&icl_reg_map),

	X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE,		&tgl_reg_map),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,		&tgl_reg_map),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,		&adl_reg_map),

	{}

};

drivers/platform/x86/intel/pmc/core.h

+2 −0
Original line number Diff line number Diff line
@@ -199,6 +199,8 @@ enum ppfear_regs { 
#define TGL_NUM_IP_IGN_ALLOWED			23

#define TGL_PMC_LPM_RES_COUNTER_STEP_X2		61	/* 30.5us * 2 */



#define ADL_PMC_SLP_S0_RES_COUNTER_OFFSET	0x1098



/*

 * Tigerlake Power Management Controller register offsets

 */