Commit bb9efa59 authored by Sandeep Maheswaram's avatar Sandeep Maheswaram Committed by Greg Kroah-Hartman
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arm64: dts: qcom: sc7280: Add USB related nodes 



Add nodes for DWC3 USB controller, QMP and HS USB PHYs in sc7280 SOC.

Reviewed-by: default avatarMatthias Kaehlcke <mka@chromium.org>
Reviewed-by: default avatarStephen Boyd <swboyd@chromium.org>
Signed-off-by: default avatarSandeep Maheswaram <sanm@codeaurora.org>
Link: https://lore.kernel.org/r/1625576413-12324-3-git-send-email-sanm@codeaurora.org


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent e516ac5d

arch/arm64/boot/dts/qcom/sc7280.dtsi

+164 −0
Original line number Diff line number Diff line
@@ -1035,6 +1035,125 @@ 
			};

		};



		usb_1_hsphy: phy@88e3000 {

			compatible = "qcom,sc7280-usb-hs-phy",

				     "qcom,usb-snps-hs-7nm-phy";

			reg = <0 0x088e3000 0 0x400>;

			status = "disabled";

			#phy-cells = <0>;



			clocks = <&rpmhcc RPMH_CXO_CLK>;

			clock-names = "ref";



			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;

		};



		usb_2_hsphy: phy@88e4000 {

			compatible = "qcom,sc7280-usb-hs-phy",

				     "qcom,usb-snps-hs-7nm-phy";

			reg = <0 0x088e4000 0 0x400>;

			status = "disabled";

			#phy-cells = <0>;



			clocks = <&rpmhcc RPMH_CXO_CLK>;

			clock-names = "ref";



			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;

		};



		usb_1_qmpphy: phy-wrapper@88e9000 {

			compatible = "qcom,sc7280-qmp-usb3-dp-phy",

				     "qcom,sm8250-qmp-usb3-dp-phy";

			reg = <0 0x088e9000 0 0x200>,

			      <0 0x088e8000 0 0x40>,

			      <0 0x088ea000 0 0x200>;

			status = "disabled";

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;



			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,

				 <&rpmhcc RPMH_CXO_CLK>,

				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;

			clock-names = "aux", "ref_clk_src", "com_aux";



			resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,

				 <&gcc GCC_USB3_PHY_PRIM_BCR>;

			reset-names = "phy", "common";



			usb_1_ssphy: usb3-phy@88e9200 {

				reg = <0 0x088e9200 0 0x200>,

				      <0 0x088e9400 0 0x200>,

				      <0 0x088e9c00 0 0x400>,

				      <0 0x088e9600 0 0x200>,

				      <0 0x088e9800 0 0x200>,

				      <0 0x088e9a00 0 0x100>;

				#clock-cells = <0>;

				#phy-cells = <0>;

				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;

				clock-names = "pipe0";

				clock-output-names = "usb3_phy_pipe_clk_src";

			};



			dp_phy: dp-phy@88ea200 {

				reg = <0 0x088ea200 0 0x200>,

				      <0 0x088ea400 0 0x200>,

				      <0 0x088eac00 0 0x400>,

				      <0 0x088ea600 0 0x200>,

				      <0 0x088ea800 0 0x200>,

				      <0 0x088eaa00 0 0x100>;

				#phy-cells = <0>;

				#clock-cells = <1>;

				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;

				clock-names = "pipe0";

				clock-output-names = "usb3_phy_pipe_clk_src";

			};

		};



		usb_2: usb@8cf8800 {

			compatible = "qcom,sc7280-dwc3", "qcom,dwc3";

			reg = <0 0x08cf8800 0 0x400>;

			status = "disabled";

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;

			dma-ranges;



			clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,

				 <&gcc GCC_USB30_SEC_MASTER_CLK>,

				 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,

				 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,

				 <&gcc GCC_USB30_SEC_SLEEP_CLK>;

			clock-names = "cfg_noc", "core", "iface","mock_utmi",

				      "sleep";



			assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,

					  <&gcc GCC_USB30_SEC_MASTER_CLK>;

			assigned-clock-rates = <19200000>, <200000000>;



			interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <&pdc 13 IRQ_TYPE_EDGE_RISING>,

				     <&pdc 12 IRQ_TYPE_EDGE_RISING>;

			interrupt-names = "hs_phy_irq",

					  "dm_hs_phy_irq", "dp_hs_phy_irq";



			power-domains = <&gcc GCC_USB30_SEC_GDSC>;



			resets = <&gcc GCC_USB30_SEC_BCR>;



			usb_2_dwc3: usb@8c00000 {

				compatible = "snps,dwc3";

				reg = <0 0x08c00000 0 0xe000>;

				interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;

				iommus = <&apps_smmu 0xa0 0x0>;

				snps,dis_u2_susphy_quirk;

				snps,dis_enblslpm_quirk;

				phys = <&usb_2_hsphy>;

				phy-names = "usb2-phy";

				maximum-speed = "high-speed";

			};

		};



		dc_noc: interconnect@90e0000 {

			reg = <0 0x090e0000 0 0x5080>;

			compatible = "qcom,sc7280-dc-noc";
@@ -1063,6 +1182,51 @@ 
			qcom,bcm-voters = <&apps_bcm_voter>;

		};



		usb_1: usb@a6f8800 {

			compatible = "qcom,sc7280-dwc3", "qcom,dwc3";

			reg = <0 0x0a6f8800 0 0x400>;

			status = "disabled";

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;

			dma-ranges;



			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,

				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,

				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,

				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,

				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;

			clock-names = "cfg_noc", "core", "iface", "mock_utmi",

				      "sleep";



			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,

					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;

			assigned-clock-rates = <19200000>, <200000000>;



			interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,

					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>,

					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,

					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",

					  "dm_hs_phy_irq", "ss_phy_irq";



			power-domains = <&gcc GCC_USB30_PRIM_GDSC>;



			resets = <&gcc GCC_USB30_PRIM_BCR>;



			usb_1_dwc3: usb@a600000 {

				compatible = "snps,dwc3";

				reg = <0 0x0a600000 0 0xe000>;

				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;

				iommus = <&apps_smmu 0xe0 0x0>;

				snps,dis_u2_susphy_quirk;

				snps,dis_enblslpm_quirk;

				phys = <&usb_1_hsphy>, <&usb_1_ssphy>;

				phy-names = "usb2-phy", "usb3-phy";

				maximum-speed = "super-speed";

			};

		};



		videocc: clock-controller@aaf0000 {

			compatible = "qcom,sc7280-videocc";

			reg = <0 0xaaf0000 0 0x10000>;