Commit bb8175a8 authored by Seungwon Jeon's avatar Seungwon Jeon Committed by Chris Ball
Browse files

mmc: sdhci: clarify DDR timing mode between SD-UHS and eMMC 



Added MMC_DDR52 as eMMC's DDR mode is distinguished from SD-UHS.

Signed-off-by: default avatarSeungwon Jeon <tgih.jun@samsung.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: default avatarChris Ball <chris@printf.net>
parent cab3a802

drivers/mmc/host/sdhci.c

+3 −1
Original line number Diff line number Diff line
@@ -1510,6 +1510,7 @@ static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) 


		/* In case of UHS-I modes, set High Speed Enable */

		if ((ios->timing == MMC_TIMING_MMC_HS200) ||

		    (ios->timing == MMC_TIMING_MMC_DDR52) ||

		    (ios->timing == MMC_TIMING_UHS_SDR50) ||

		    (ios->timing == MMC_TIMING_UHS_SDR104) ||

		    (ios->timing == MMC_TIMING_UHS_DDR50) ||
@@ -1570,7 +1571,8 @@ static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) 
				ctrl_2 |= SDHCI_CTRL_UHS_SDR25;

			else if (ios->timing == MMC_TIMING_UHS_SDR50)

				ctrl_2 |= SDHCI_CTRL_UHS_SDR50;

			else if (ios->timing == MMC_TIMING_UHS_DDR50)

			else if ((ios->timing == MMC_TIMING_UHS_DDR50) ||

				 (ios->timing == MMC_TIMING_MMC_DDR52))

				ctrl_2 |= SDHCI_CTRL_UHS_DDR50;

			sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);

		}