Commit bb656add authored by Bard Liao's avatar Bard Liao Committed by Mark Brown
Browse files

ASoC: rt5645: Add JD function support 



rt5645 codec support jack detection function. The patch will set
related registers if JD function is used.

Signed-off-by: default avatarBard Liao <bardliao@realtek.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 0b2e4959

include/sound/rt5645.h

+3 −0
Original line number Diff line number Diff line
@@ -23,6 +23,9 @@ struct rt5645_platform_data { 


	unsigned int hp_det_gpio;

	bool gpio_hp_det_active_high;



	/* true if codec's jd function is used */

	bool en_jd_func;

};



#endif

sound/soc/codecs/rt5645.c

+20 −0
Original line number Diff line number Diff line
@@ -2203,6 +2203,13 @@ static int rt5645_probe(struct snd_soc_codec *codec) 


	snd_soc_update_bits(codec, RT5645_CHARGE_PUMP, 0x0300, 0x0200);



	/* for JD function */

	if (rt5645->pdata.en_jd_func) {

		snd_soc_dapm_force_enable_pin(&codec->dapm, "JD Power");

		snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");

		snd_soc_dapm_sync(&codec->dapm);

	}



	return 0;

}
@@ -2436,6 +2443,19 @@ static int rt5645_i2c_probe(struct i2c_client *i2c, 


	}



	if (rt5645->pdata.en_jd_func) {

		regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,

			RT5645_IRQ_CLK_GATE_CTRL | RT5645_MICINDET_MANU,

			RT5645_IRQ_CLK_GATE_CTRL | RT5645_MICINDET_MANU);

		regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,

			RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN);

		regmap_update_bits(rt5645->regmap, RT5645_JD_CTRL3,

			RT5645_JD_CBJ_EN | RT5645_JD_CBJ_POL,

			RT5645_JD_CBJ_EN | RT5645_JD_CBJ_POL);

		regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,

			RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);

	}



	if (rt5645->i2c->irq) {

		ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq,

			IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING

sound/soc/codecs/rt5645.h

+5 −0
Original line number Diff line number Diff line
@@ -1348,6 +1348,8 @@ 
#define RT5645_PWR_CLK25M_SFT			4

#define RT5645_PWR_CLK25M_PD			(0x0 << 4)

#define RT5645_PWR_CLK25M_PU			(0x1 << 4)

#define RT5645_IRQ_CLK_MCLK			(0x0 << 3)

#define RT5645_IRQ_CLK_INT			(0x1 << 3)



/* VAD Control 4 (0x9d) */

#define RT5645_VAD_SEL_MASK			(0x3 << 8)
@@ -2116,6 +2118,9 @@ enum { 
#define RT5645_RXDP2_SEL_ADC			(0x1 << 3)

#define RT5645_RXDP2_SEL_SFT			(3)



/* General Control3 (0xfc) */

#define RT5645_IRQ_CLK_GATE_CTRL		(0x1 << 11)

#define RT5645_MICINDET_MANU			(0x1 << 7)



/* Vendor ID (0xfd) */

#define RT5645_VER_C				0x2