Commit baf1fb26 authored by Matthew Barth's avatar Matthew Barth Committed by Joel Stanley
Browse files

ARM: dts: aspeed: everest: Add pca9552 fan presence 



Add the pca9552 at address 0x61 on i2c14 behind mux0 channel 3 with the
4 GPIO fan presence inputs.

Signed-off-by: default avatarMatthew Barth <msbarth@us.ibm.com>
Signed-off-by: default avatarEddie James <eajames@linux.ibm.com>
Reviewed-by: default avatarBrandon Wyman <bjwyman@gmail.com>
Link: https://lore.kernel.org/r/20210329150020.13632-16-eajames@linux.ibm.com


Signed-off-by: default avatarJoel Stanley <joel@jms.id.au>
parent d9406d17

arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts

+128 −0
Original line number Diff line number Diff line
@@ -171,6 +171,37 @@ 
			reg = <0xbf000000 0x01000000>; /* 16M */

		};

	};



	gpio-keys-polled {

		compatible = "gpio-keys-polled";

		#address-cells = <1>;

		#size-cells = <0>;

		poll-interval = <1000>;



		fan0-presence {

			label = "fan0-presence";

			gpios = <&pca0 15 GPIO_ACTIVE_LOW>;

			linux,code = <15>;

		};



		fan1-presence {

			label = "fan1-presence";

			gpios = <&pca0 14 GPIO_ACTIVE_LOW>;

			linux,code = <14>;

		};



		fan2-presence {

			label = "fan2-presence";

			gpios = <&pca0 13 GPIO_ACTIVE_LOW>;

			linux,code = <13>;

		};



		fan3-presence {

			label = "fan3-presence";

			gpios = <&pca0 12 GPIO_ACTIVE_LOW>;

			linux,code = <12>;

		};

	};

};



&i2c0 {
@@ -540,6 +571,103 @@ 
					tach-pulses = <2>;

				};

			};



			pca0: pca9552@61 {

				compatible = "nxp,pca9552";

				reg = <0x61>;



				gpio-controller;

				#gpio-cells = <2>;



				gpio-line-names =

					"","","","",

					"","","","",

					"","","","",

					"presence-fan3",

					"presence-fan2",

					"presence-fan1",

					"presence-fan0";



				gpio@0 {

					reg = <0>;

					type = <PCA955X_TYPE_GPIO>;

				};



				gpio@1 {

					reg = <1>;

					type = <PCA955X_TYPE_GPIO>;

				};



				gpio@2 {

					reg = <2>;

					type = <PCA955X_TYPE_GPIO>;

				};



				gpio@3 {

					reg = <3>;

					type = <PCA955X_TYPE_GPIO>;

				};



				gpio@4 {

					reg = <4>;

					type = <PCA955X_TYPE_GPIO>;

				};



				gpio@5 {

					reg = <5>;

					type = <PCA955X_TYPE_GPIO>;

				};



				gpio@6 {

					reg = <6>;

					type = <PCA955X_TYPE_GPIO>;

				};



				gpio@7 {

					reg = <7>;

					type = <PCA955X_TYPE_GPIO>;

				};



				gpio@8 {

					reg = <8>;

					type = <PCA955X_TYPE_GPIO>;

				};



				gpio@9 {

					reg = <9>;

					type = <PCA955X_TYPE_GPIO>;

				};



				gpio@10 {

					reg = <10>;

					type = <PCA955X_TYPE_GPIO>;

				};



				gpio@11 {

					reg = <11>;

					type = <PCA955X_TYPE_GPIO>;

				};



				gpio@12 {

					reg = <12>;

					type = <PCA955X_TYPE_GPIO>;

				};



				gpio@13 {

					reg = <13>;

					type = <PCA955X_TYPE_GPIO>;

				};



				gpio@14 {

					reg = <14>;

					type = <PCA955X_TYPE_GPIO>;

				};



				gpio@15 {

					reg = <15>;

					type = <PCA955X_TYPE_GPIO>;

				};

			};

		};

	};