Commit baea429d authored by Tvrtko Ursulin's avatar Tvrtko Ursulin
Browse files

drm/i915: Move i915_gem_chipset_flush to intel_gt 



This aligns better with the rest of restructuring.

v2:
 * Move call out of line. (Chris)

Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Suggested-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190621070811.7006-24-tvrtko.ursulin@linux.intel.com
parent a1c8a09e

drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c

+3 −2
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ 


#include "gem/i915_gem_ioctls.h"

#include "gt/intel_context.h"

#include "gt/intel_gt.h"

#include "gt/intel_gt_pm.h"



#include "i915_gem_ioctls.h"
@@ -994,7 +995,7 @@ static void reloc_gpu_flush(struct reloc_cache *cache) 
	__i915_gem_object_flush_map(cache->rq->batch->obj, 0, cache->rq_size);

	i915_gem_object_unpin_map(cache->rq->batch->obj);



	i915_gem_chipset_flush(cache->rq->i915);

	intel_gt_chipset_flush(cache->rq->engine->gt);



	i915_request_add(cache->rq);

	cache->rq = NULL;
@@ -1954,7 +1955,7 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb) 
	eb->exec = NULL;



	/* Unconditionally flush any chipset caches (for streaming writes). */

	i915_gem_chipset_flush(eb->i915);

	intel_gt_chipset_flush(eb->engine->gt);

	return 0;



err_skip:

drivers/gpu/drm/i915/gem/i915_gem_phys.c

+2 −1
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include <drm/drm_legacy.h> /* for drm_pci.h! */

#include <drm/drm_pci.h>



#include "gt/intel_gt.h"

#include "i915_drv.h"

#include "i915_gem_object.h"

#include "i915_scatterlist.h"
@@ -60,7 +61,7 @@ static int i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) 
		vaddr += PAGE_SIZE;

	}



	i915_gem_chipset_flush(to_i915(obj->base.dev));

	intel_gt_chipset_flush(&to_i915(obj->base.dev)->gt);



	st = kmalloc(sizeof(*st), GFP_KERNEL);

	if (!st) {

drivers/gpu/drm/i915/gem/selftests/huge_pages.c

+3 −1
Original line number Diff line number Diff line
@@ -10,6 +10,8 @@ 


#include "gem/i915_gem_pm.h"



#include "gt/intel_gt.h"



#include "igt_gem_utils.h"

#include "mock_context.h"
@@ -926,7 +928,7 @@ gpu_write_dw(struct i915_vma *vma, u64 offset, u32 val) 
	}



	*cmd = MI_BATCH_BUFFER_END;

	i915_gem_chipset_flush(i915);

	intel_gt_chipset_flush(vma->vm->gt);



	i915_gem_object_unpin_map(obj);

drivers/gpu/drm/i915/gt/intel_gt.c

+8 −1
Original line number Diff line number Diff line
@@ -180,7 +180,7 @@ void intel_gt_flush_ggtt_writes(struct intel_gt *gt) 
	if (INTEL_INFO(i915)->has_coherent_ggtt)

		return;



	i915_gem_chipset_flush(i915);

	intel_gt_chipset_flush(gt);



	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {

		struct intel_uncore *uncore = gt->uncore;
@@ -191,3 +191,10 @@ void intel_gt_flush_ggtt_writes(struct intel_gt *gt) 
		spin_unlock_irq(&uncore->lock);

	}

}



void intel_gt_chipset_flush(struct intel_gt *gt)

{

	wmb();

	if (INTEL_GEN(gt->i915) < 6)

		intel_gtt_chipset_flush();

}

drivers/gpu/drm/i915/gt/intel_gt.h

+1 −0
Original line number Diff line number Diff line
@@ -18,5 +18,6 @@ void intel_gt_clear_error_registers(struct intel_gt *gt, 
				    intel_engine_mask_t engine_mask);



void intel_gt_flush_ggtt_writes(struct intel_gt *gt);

void intel_gt_chipset_flush(struct intel_gt *gt);



#endif /* __INTEL_GT_H__ */