Commit bae83341 authored Feb 11, 2023 by Arınç ÜNAL Committed by Thomas Bogendoerfer Feb 17, 2023

mips: dts: ralink: mt7621: add port@5 as CPU port

On MT7621AT, MT7621DAT, and MT7621ST SoCs, port 5 of the MT7530 switch is
connected to the second MAC of the SoC as a CPU port. Add the port and set
up the second MAC on the bindings. Revert PHY muxing on GB-PC1.

There's an external PHY connected to the second MAC of the SoC on GB-PC2,
therefore, disable port@5 for this device.

Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

parent 09e61efd

arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts

+5 −11

Original line number	Diff line number	Diff line
		@@ -91,22 +91,16 @@
		status = "okay";
		};

		&gmac1 {
		status = "okay";
		phy-handle = <&ethphy4>;
		};

		&mdio {
		ethphy4: ethernet-phy@4 {
		reg = <4>;
		};
		};

		&switch0 {
		ports {
		port@0 {
		status = "okay";
		label = "ethblack";
		};

		port@4 {
		status = "okay";
		label = "ethblue";
		};
		};
		};

arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts

+8 −1

Original line number	Diff line number	Diff line
		@@ -112,9 +112,12 @@
		};

		&gmac1 {
		status = "okay";
		phy-mode = "rgmii-rxid";
		phy-handle = <&ethphy5>;

		fixed-link {
		status = "disabled";
		};
		};

		&mdio {
		@@ -134,5 +137,9 @@
		status = "okay";
		label = "ethblue";
		};

		port@5 {
		status = "disabled";
		};
		};
		};

arch/mips/boot/dts/ralink/mt7621.dtsi

+18 −1

Original line number	Diff line number	Diff line
		@@ -332,8 +332,13 @@
		gmac1: mac@1 {
		compatible = "mediatek,eth-mac";
		reg = <1>;
		status = "disabled";
		phy-mode = "rgmii";

		fixed-link {
		speed = <1000>;
		full-duplex;
		pause;
		};
		};

		mdio: mdio-bus {
		@@ -384,6 +389,18 @@
		label = "swp4";
		};

		port@5 {
		reg = <5>;
		ethernet = <&gmac1>;
		phy-mode = "rgmii";

		fixed-link {
		speed = <1000>;
		full-duplex;
		pause;
		};
		};

		port@6 {
		reg = <6>;
		ethernet = <&gmac0>;