Commit bae19fdd authored by Sandipan Das's avatar Sandipan Das Committed by Peter Zijlstra
Browse files

perf/x86/amd/core: Fix reloading events for SVM 



Commit 1018faa6 ("perf/x86/kvm: Fix Host-Only/Guest-Only
counting with SVM disabled") addresses an issue in which the
Host-Only bit in the counter control registers needs to be
masked off when SVM is not enabled.

The events need to be reloaded whenever SVM is enabled or
disabled for a CPU and this requires the PERF_CTL registers
to be reprogrammed using {enable,disable}_all(). However,
PerfMonV2 variants of these functions do not reprogram the
PERF_CTL registers. Hence, the legacy enable_all() function
should also be called.

Fixes: 9622e67e ("perf/x86/amd/core: Add PerfMonV2 counter control")
Reported-by: default avatarLike Xu <likexu@tencent.com>
Signed-off-by: default avatarSandipan Das <sandipan.das@amd.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20220518084327.464005-1-sandipan.das@amd.com
parent 841b51e4

arch/x86/events/amd/core.c

+20 −4
Original line number Original line Diff line number Diff line
@@ -1472,6 +1472,24 @@ __init int amd_pmu_init(void) 
	return 0;

	return 0;

}

}





static inline void amd_pmu_reload_virt(void)

{

	if (x86_pmu.version >= 2) {

		/*

		 * Clear global enable bits, reprogram the PERF_CTL

		 * registers with updated perf_ctr_virt_mask and then

		 * set global enable bits once again

		 */

		amd_pmu_v2_disable_all();

		amd_pmu_enable_all(0);

		amd_pmu_v2_enable_all(0);

		return;

	}



	amd_pmu_disable_all();

	amd_pmu_enable_all(0);

}



void amd_pmu_enable_virt(void)

void amd_pmu_enable_virt(void)

{

{

	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);

	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
@@ -1479,8 +1497,7 @@ void amd_pmu_enable_virt(void) 
	cpuc->perf_ctr_virt_mask = 0;

	cpuc->perf_ctr_virt_mask = 0;





	/* Reload all events */

	/* Reload all events */

	amd_pmu_disable_all();

	amd_pmu_reload_virt();

	x86_pmu_enable_all(0);

}

}

EXPORT_SYMBOL_GPL(amd_pmu_enable_virt);

EXPORT_SYMBOL_GPL(amd_pmu_enable_virt);
@@ -1497,7 +1514,6 @@ void amd_pmu_disable_virt(void) 
	cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY;

	cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY;





	/* Reload all events */

	/* Reload all events */

	amd_pmu_disable_all();

	amd_pmu_reload_virt();

	x86_pmu_enable_all(0);

}

}

EXPORT_SYMBOL_GPL(amd_pmu_disable_virt);
 
EXPORT_SYMBOL_GPL(amd_pmu_disable_virt);