Commit badd9f19 authored by Jean-Philippe Brucker's avatar Jean-Philippe Brucker Committed by Bjorn Helgaas
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dt-bindings: Add "external-facing" PCIe port property 



Provide a way for the firmware to tell the OS which devices are external to
the machine and therefore untrusted.  The property can describe for example
Thunderbolt and other user-accessible ports, which should always have the
strongest IOMMU protection.

Signed-off-by: default avatarJean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarGrant Likely <grant.likely@arm.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Reviewed-by: default avatarRobin Murphy <robin.murphy@arm.com>
parent 658eec83

Documentation/devicetree/bindings/pci/pci.txt

+50 −0
Original line number Diff line number Diff line
@@ -24,3 +24,53 @@ driver implementation may support the following properties: 
   unsupported link speed, for instance, trying to do training for

   unsupported link speed, etc.  Must be '4' for gen4, '3' for gen3, '2'

   for gen2, and '1' for gen1. Any other values are invalid.



PCI-PCI Bridge properties

-------------------------



PCIe root ports and switch ports may be described explicitly in the device

tree, as children of the host bridge node. Even though those devices are

discoverable by probing, it might be necessary to describe properties that

aren't provided by standard PCIe capabilities.



Required properties:



- reg:

   Identifies the PCI-PCI bridge. As defined in the IEEE Std 1275-1994

   document, it is a five-cell address encoded as (phys.hi phys.mid

   phys.lo size.hi size.lo). phys.hi should contain the device's BDF as

   0b00000000 bbbbbbbb dddddfff 00000000. The other cells should be zero.



   The bus number is defined by firmware, through the standard bridge

   configuration mechanism. If this port is a switch port, then firmware

   allocates the bus number and writes it into the Secondary Bus Number

   register of the bridge directly above this port. Otherwise, the bus

   number of a root port is the first number in the bus-range property,

   defaulting to zero.



   If firmware leaves the ARI Forwarding Enable bit set in the bridge

   above this port, then phys.hi contains the 8-bit function number as

   0b00000000 bbbbbbbb ffffffff 00000000. Note that the PCIe specification

   recommends that firmware only leaves ARI enabled when it knows that the

   OS is ARI-aware.



Optional properties:



- external-facing:

   When present, the port is external-facing. All bridges and endpoints

   downstream of this port are external to the machine. The OS can, for

   example, use this information to identify devices that cannot be

   trusted with relaxed DMA protection, as users could easily attach

   malicious devices to this port.



Example:



pcie@10000000 {

	compatible = "pci-host-ecam-generic";

	...

	pcie@0008 {

		/* Root port 00:01.0 is external-facing */

		reg = <0x00000800 0 0 0 0>;

		external-facing;

	};

};