Commit bada0389 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v5.16-tag2' of... 

Merge tag 'renesas-clk-for-v5.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add SPI Multi I/O Bus and SDHI clocks and resets on RZ/G2L
 - Add SPI Multi I/O Bus (RPC) clocks on R-Car V3U
 - Add MediaLB clocks on R-Car H3, M3-W/W+, and M3-N

* tag 'renesas-clk-for-v5.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a779[56]x: Add MLP clocks
  clk: renesas: r9a07g044: Add SDHI clock and reset entries
  clk: renesas: rzg2l: Add SDHI clk mux support
  clk: renesas: r8a779a0: Add RPC support
  clk: renesas: cpg-lib: Move RPC clock registration to the library
  clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Controller
parents e974872e 2bd9feed

drivers/clk/renesas/r8a7795-cpg-mssr.c

+1 −0
Original line number Diff line number Diff line
@@ -229,6 +229,7 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { 
	DEF_MOD("lvds",			 727,	R8A7795_CLK_S0D4),

	DEF_MOD("hdmi1",		 728,	R8A7795_CLK_HDMI),

	DEF_MOD("hdmi0",		 729,	R8A7795_CLK_HDMI),

	DEF_MOD("mlp",			 802,	R8A7795_CLK_S2D1),

	DEF_MOD("vin7",			 804,	R8A7795_CLK_S0D2),

	DEF_MOD("vin6",			 805,	R8A7795_CLK_S0D2),

	DEF_MOD("vin5",			 806,	R8A7795_CLK_S0D2),

drivers/clk/renesas/r8a7796-cpg-mssr.c

+1 −0
Original line number Diff line number Diff line
@@ -207,6 +207,7 @@ static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = { 
	DEF_MOD("du0",			 724,	R8A7796_CLK_S2D1),

	DEF_MOD("lvds",			 727,	R8A7796_CLK_S2D1),

	DEF_MOD("hdmi0",		 729,	R8A7796_CLK_HDMI),

	DEF_MOD("mlp",			 802,	R8A7796_CLK_S2D1),

	DEF_MOD("vin7",			 804,	R8A7796_CLK_S0D2),

	DEF_MOD("vin6",			 805,	R8A7796_CLK_S0D2),

	DEF_MOD("vin5",			 806,	R8A7796_CLK_S0D2),

drivers/clk/renesas/r8a77965-cpg-mssr.c

+1 −0
Original line number Diff line number Diff line
@@ -205,6 +205,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { 
	DEF_MOD("lvds",			727,	R8A77965_CLK_S2D1),

	DEF_MOD("hdmi0",		729,	R8A77965_CLK_HDMI),



	DEF_MOD("mlp",			802,	R8A77965_CLK_S2D1),

	DEF_MOD("vin7",			804,	R8A77965_CLK_S0D2),

	DEF_MOD("vin6",			805,	R8A77965_CLK_S0D2),

	DEF_MOD("vin5",			806,	R8A77965_CLK_S0D2),

drivers/clk/renesas/r8a779a0-cpg-mssr.c

+32 −0
Original line number Diff line number Diff line
@@ -37,6 +37,9 @@ enum rcar_r8a779a0_clk_types { 
	CLK_TYPE_R8A779A0_SD,

	CLK_TYPE_R8A779A0_MDSEL,	/* Select parent/divider using mode pin */

	CLK_TYPE_R8A779A0_OSC,	/* OSC EXTAL predivider and fixed divider */

	CLK_TYPE_R8A779A0_RPCSRC,

	CLK_TYPE_R8A779A0_RPC,

	CLK_TYPE_R8A779A0_RPCD2,

};



struct rcar_r8a779a0_cpg_pll_config {
@@ -125,6 +128,10 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { 
	DEF_FIXED(".s3",		CLK_S3,		CLK_PLL1_DIV2,	4, 1),

	DEF_FIXED(".sdsrc",		CLK_SDSRC,	CLK_PLL5_DIV4,	1, 1),

	DEF_RATE(".oco",		CLK_OCO,	32768),

	DEF_BASE(".rpcsrc",	 CLK_RPCSRC,	   CLK_TYPE_R8A779A0_RPCSRC, CLK_PLL5),

	DEF_BASE("rpc",		 R8A779A0_CLK_RPC, CLK_TYPE_R8A779A0_RPC, CLK_RPCSRC),

	DEF_BASE("rpcd2",	 R8A779A0_CLK_RPCD2, CLK_TYPE_R8A779A0_RPCD2,

		 R8A779A0_CLK_RPC),



	/* Core Clock Outputs */

	DEF_Z("z0",		R8A779A0_CLK_Z0,	CLK_PLL20,	2, 0),
@@ -200,6 +207,7 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { 
	DEF_MOD("msi3",		621,	R8A779A0_CLK_MSO),

	DEF_MOD("msi4",		622,	R8A779A0_CLK_MSO),

	DEF_MOD("msi5",		623,	R8A779A0_CLK_MSO),

	DEF_MOD("rpc-if",	629,	R8A779A0_CLK_RPCD2),

	DEF_MOD("scif0",	702,	R8A779A0_CLK_S1D8),

	DEF_MOD("scif1",	703,	R8A779A0_CLK_S1D8),

	DEF_MOD("scif3",	704,	R8A779A0_CLK_S1D8),
@@ -414,6 +422,15 @@ static struct clk * __init cpg_z_clk_register(const char *name, 
	return clk;

}



/*

 * RPC Clocks

 */

#define CPG_RPCCKCR 0x874



static const struct clk_div_table cpg_rpcsrc_div_table[] = {

	{ 0, 4 }, { 1, 6 }, { 2, 5 }, { 3, 6 }, { 0, 0 },

};



static struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,

	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,

	struct clk **clks, void __iomem *base,
@@ -481,6 +498,21 @@ static struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev, 
		div = cpg_pll_config->osc_prediv * core->div;

		break;



	case CLK_TYPE_R8A779A0_RPCSRC:

		return clk_register_divider_table(NULL, core->name,

						  __clk_get_name(parent), 0,

						  base + CPG_RPCCKCR, 3, 2, 0,

						  cpg_rpcsrc_div_table,

						  &cpg_lock);



	case CLK_TYPE_R8A779A0_RPC:

		return cpg_rpc_clk_register(core->name, base + CPG_RPCCKCR,

					    __clk_get_name(parent), notifiers);



	case CLK_TYPE_R8A779A0_RPCD2:

		return cpg_rpcd2_clk_register(core->name, base + CPG_RPCCKCR,

					      __clk_get_name(parent));



	default:

		return ERR_PTR(-EINVAL);

	}

drivers/clk/renesas/r9a07g044-cpg.c

+54 −0
Original line number Diff line number Diff line
@@ -29,10 +29,14 @@ enum clk_ids { 
	CLK_PLL2_DIV16,

	CLK_PLL2_DIV20,

	CLK_PLL3,

	CLK_PLL3_400,

	CLK_PLL3_533,

	CLK_PLL3_DIV2,

	CLK_PLL3_DIV2_4,

	CLK_PLL3_DIV2_4_2,

	CLK_PLL3_DIV4,

	CLK_SEL_PLL3_3,

	CLK_DIV_PLL3_C,

	CLK_PLL4,

	CLK_PLL5,

	CLK_PLL5_FOUT3,
@@ -40,6 +44,12 @@ enum clk_ids { 
	CLK_PLL6,

	CLK_PLL6_250,

	CLK_P1_DIV2,

	CLK_PLL2_800,

	CLK_PLL2_SDHI_533,

	CLK_PLL2_SDHI_400,

	CLK_PLL2_SDHI_266,

	CLK_SD0_DIV4,

	CLK_SD1_DIV4,



	/* Module Clocks */

	MOD_CLK_BASE,
@@ -56,7 +66,9 @@ static const struct clk_div_table dtable_1_32[] = { 
};



/* Mux clock tables */

static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };

static const char * const sel_pll6_2[]	= { ".pll6_250", ".pll5_250" };

static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };



static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {

	/* External Clock Inputs */
@@ -68,6 +80,8 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { 
	DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),

	DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2),

	DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2),

	DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4),

	DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),



	DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),

	DEF_FIXED(".pll5_fout3", CLK_PLL5_FOUT3, CLK_PLL5, 1, 6),
@@ -75,6 +89,11 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { 
	DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),



	DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),

	DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2),

	DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3),

	DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2),

	DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2),



	DEF_FIXED(".pll2_div16", CLK_PLL2_DIV16, CLK_PLL2, 1, 16),

	DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20),
@@ -82,6 +101,10 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { 
	DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),

	DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),

	DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),

	DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3,

		sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY),

	DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3,

		DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),



	DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2),

	DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
@@ -101,6 +124,14 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { 
	DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),

	DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2,

		sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK),

	DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),

	DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),

	DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0,

		   sel_shdi, ARRAY_SIZE(sel_shdi)),

	DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1,

		   sel_shdi, ARRAY_SIZE(sel_shdi)),

	DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),

	DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),

};



static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
@@ -114,6 +145,26 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { 
				0x52c, 0),

	DEF_MOD("dmac_pclk",	R9A07G044_DMAC_PCLK, CLK_P1_DIV2,

				0x52c, 1),

	DEF_MOD("spi_clk2",	R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1,

				0x550, 0),

	DEF_MOD("spi_clk",	R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0,

				0x550, 1),

	DEF_MOD("sdhi0_imclk",	R9A07G044_SDHI0_IMCLK, CLK_SD0_DIV4,

				0x554, 0),

	DEF_MOD("sdhi0_imclk2",	R9A07G044_SDHI0_IMCLK2, CLK_SD0_DIV4,

				0x554, 1),

	DEF_MOD("sdhi0_clk_hs",	R9A07G044_SDHI0_CLK_HS, R9A07G044_CLK_SD0,

				0x554, 2),

	DEF_MOD("sdhi0_aclk",	R9A07G044_SDHI0_ACLK, R9A07G044_CLK_P1,

				0x554, 3),

	DEF_MOD("sdhi1_imclk",	R9A07G044_SDHI1_IMCLK, CLK_SD1_DIV4,

				0x554, 4),

	DEF_MOD("sdhi1_imclk2",	R9A07G044_SDHI1_IMCLK2, CLK_SD1_DIV4,

				0x554, 5),

	DEF_MOD("sdhi1_clk_hs",	R9A07G044_SDHI1_CLK_HS, R9A07G044_CLK_SD1,

				0x554, 6),

	DEF_MOD("sdhi1_aclk",	R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1,

				0x554, 7),

	DEF_MOD("ssi0_pclk",	R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,

				0x570, 0),

	DEF_MOD("ssi0_sfr",	R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
@@ -182,6 +233,9 @@ static struct rzg2l_reset r9a07g044_resets[] = { 
	DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),

	DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),

	DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),

	DEF_RST(R9A07G044_SPI_RST, 0x850, 0),

	DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0),

	DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1),

	DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),

	DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),

	DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),