Commit babbdf5b authored by Aric Cyr's avatar Aric Cyr Committed by Alex Deucher
Browse files

drm/amd/display: Round KHz up when calculating clock requests 



[Why]
When requesting clocks from SMU which takes MHz inputs, DC will round
down KHz when converting to MHz, thus potentially requesting too low a
clock value.

[How]
Round up (ceil) when converting KHz to MHz for clock requests to SMU.

Signed-off-by: default avatarAric Cyr <aric.cyr@amd.com>
Reviewed-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cc590fd2

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

+6 −6
Original line number Diff line number Diff line
@@ -264,9 +264,9 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base, 
		if (pp_smu->set_hard_min_fclk_by_freq &&

				pp_smu->set_hard_min_dcfclk_by_freq &&

				pp_smu->set_min_deep_sleep_dcfclk) {

			pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, new_clocks->fclk_khz / 1000);

			pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, new_clocks->dcfclk_khz / 1000);

			pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);

			pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz));

			pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz));

			pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_deep_sleep_khz));

		}

	}
@@ -284,9 +284,9 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base, 
		if (pp_smu->set_hard_min_fclk_by_freq &&

				pp_smu->set_hard_min_dcfclk_by_freq &&

				pp_smu->set_min_deep_sleep_dcfclk) {

			pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, new_clocks->fclk_khz / 1000);

			pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, new_clocks->dcfclk_khz / 1000);

			pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);

			pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz));

			pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz));

			pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_deep_sleep_khz));

		}

	}

}

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

+2 −2
Original line number Diff line number Diff line
@@ -130,7 +130,7 @@ int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_di 
	actual_dispclk_set_mhz = rv1_vbios_smu_send_msg_with_param(

			clk_mgr,

			VBIOSSMC_MSG_SetDispclkFreq,

			requested_dispclk_khz / 1000);

			khz_to_mhz_ceil(requested_dispclk_khz));



	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {

		if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
@@ -150,7 +150,7 @@ int rv1_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) 
	actual_dprefclk_set_mhz = rv1_vbios_smu_send_msg_with_param(

			clk_mgr,

			VBIOSSMC_MSG_SetDprefclkFreq,

			clk_mgr->base.dprefclk_khz / 1000);

			khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz));



	/* TODO: add code for programing DP DTO, currently this is down by command table */

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

+6 −6
Original line number Diff line number Diff line
@@ -253,20 +253,20 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, 
	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {

		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;

		if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq)

			pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_khz / 1000);

			pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));

	}



	if (should_set_clock(safe_to_lower,

			new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {

		clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;

		if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk)

			pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_deep_sleep_khz / 1000);

			pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));

	}



	if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) {

		clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;

		if (pp_smu && pp_smu->set_hard_min_socclk_by_freq)

			pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.socclk_khz / 1000);

			pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.socclk_khz));

	}



	total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
@@ -281,7 +281,7 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, 
	if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {

		clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;

		if (pp_smu && pp_smu->set_hard_min_uclk_by_freq)

			pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dramclk_khz / 1000);

			pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));

	}



	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
@@ -306,7 +306,7 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, 


		clk_mgr_base->clks.disp_dpp_voltage_level_khz = new_clocks->disp_dpp_voltage_level_khz;

		if (pp_smu && pp_smu->set_voltage_by_freq)

			pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.disp_dpp_voltage_level_khz / 1000);

			pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.disp_dpp_voltage_level_khz));

	}



	if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
@@ -502,7 +502,7 @@ static void dcn2_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc 


	if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) {

		clk_mgr_base->clks.phyclk_khz = max_phyclk_req;

		pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000);

		pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, khz_to_mhz_ceil(clk_mgr_base->clks.phyclk_khz));

	}

}

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

+8 −8
Original line number Diff line number Diff line
@@ -126,7 +126,7 @@ int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dis 
	actual_dispclk_set_mhz = rn_vbios_smu_send_msg_with_param(

			clk_mgr,

			VBIOSSMC_MSG_SetDispclkFreq,

			requested_dispclk_khz / 1000);

			khz_to_mhz_ceil(requested_dispclk_khz));



	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {

		if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
@@ -138,7 +138,7 @@ int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dis 


	// pmfw always set clock more than or equal requested clock

	if (!IS_DIAG_DC(dc->ctx->dce_environment))

		ASSERT(actual_dispclk_set_mhz >= requested_dispclk_khz / 1000);

		ASSERT(actual_dispclk_set_mhz >= khz_to_mhz_ceil(requested_dispclk_khz));



	return actual_dispclk_set_mhz * 1000;

}
@@ -150,7 +150,7 @@ int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) 
	actual_dprefclk_set_mhz = rn_vbios_smu_send_msg_with_param(

			clk_mgr,

			VBIOSSMC_MSG_SetDprefclkFreq,

			clk_mgr->base.dprefclk_khz / 1000);

			khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz));



	/* TODO: add code for programing DP DTO, currently this is down by command table */
@@ -167,7 +167,7 @@ int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int reque 
	actual_dcfclk_set_mhz = rn_vbios_smu_send_msg_with_param(

			clk_mgr,

			VBIOSSMC_MSG_SetHardMinDcfclkByFreq,

			requested_dcfclk_khz / 1000);

			khz_to_mhz_ceil(requested_dcfclk_khz));



	return actual_dcfclk_set_mhz * 1000;

}
@@ -182,7 +182,7 @@ int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int 
	actual_min_ds_dcfclk_mhz = rn_vbios_smu_send_msg_with_param(

			clk_mgr,

			VBIOSSMC_MSG_SetMinDeepSleepDcfclk,

			requested_min_ds_dcfclk_khz / 1000);

			khz_to_mhz_ceil(requested_min_ds_dcfclk_khz));



	return actual_min_ds_dcfclk_mhz * 1000;

}
@@ -192,7 +192,7 @@ void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phy 
	rn_vbios_smu_send_msg_with_param(

			clk_mgr,

			VBIOSSMC_MSG_SetPhyclkVoltageByFreq,

			requested_phyclk_khz / 1000);

			khz_to_mhz_ceil(requested_phyclk_khz));

}



int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)
@@ -203,10 +203,10 @@ int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_ 
	actual_dppclk_set_mhz = rn_vbios_smu_send_msg_with_param(

			clk_mgr,

			VBIOSSMC_MSG_SetDppclkFreq,

			requested_dpp_khz / 1000);

			khz_to_mhz_ceil(requested_dpp_khz));



	if (!IS_DIAG_DC(dc->ctx->dce_environment))

		ASSERT(actual_dppclk_set_mhz >= requested_dpp_khz / 1000);

		ASSERT(actual_dppclk_set_mhz >= khz_to_mhz_ceil(requested_dpp_khz));



	return actual_dppclk_set_mhz * 1000;

}

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

+15 −10
Original line number Diff line number Diff line
@@ -280,12 +280,12 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base, 


	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {

		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;

		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCEFCLK, clk_mgr_base->clks.dcfclk_khz / 1000);

		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCEFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));

	}



	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {

		clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;

		dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz / 1000);

		dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));

	}



	if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
@@ -313,20 +313,20 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base, 
	/* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */

	if (clk_mgr_base->clks.p_state_change_support &&

			(update_uclk || !clk_mgr_base->clks.prev_p_state_change_support))

		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, clk_mgr_base->clks.dramclk_khz / 1000);

		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));



	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {

		if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)

			dpp_clock_lowered = true;



		clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;

		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, clk_mgr_base->clks.dppclk_khz / 1000);

		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));

		update_dppclk = true;

	}



	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {

		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;

		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000);

		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz));

		update_dispclk = true;

	}
@@ -392,13 +392,18 @@ static void dcn3_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_ 
	if (!clk_mgr->smu_present)

		return;



	if (current_mode)

	if (current_mode) {

		if (clk_mgr_base->clks.p_state_change_support)

			dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,

				clk_mgr_base->clks.dramclk_khz / 1000);

					khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));

		else

			dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,

					clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);

	} else {

		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,

				clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);

	}

}



/* Set max memclk to highest DPM value */

static void dcn3_set_hard_max_memclk(struct clk_mgr *clk_mgr_base)
@@ -485,7 +490,7 @@ static void dcn30_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct d 


	if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) {

		clk_mgr_base->clks.phyclk_khz = max_phyclk_req;

		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000);

		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, khz_to_mhz_ceil(clk_mgr_base->clks.phyclk_khz));

	}

}