Commit bab6ffa2 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'fpga-for-5.19-rc1' of... 

Merge tag 'fpga-for-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga

 into char-misc-next

Moritz writes:

FPGA Manager changes for 5.19-rc1

FPGA Manager

- My change moves the linux-fpga repository to a shared
  location w/ shared responsibilities between maintainers
- Nava's changes fix coding style and kernel-docs

DFL

- Matthew's change allows ports to be linked to FMEs.
- Tianfei's changes clean up some documentation and
  ensure the feature type is checked before parsing IRQs

All patches have been reviewed on the mailing list, and have been in the
last linux-next releases (as part of our for-next branch).

Signed-off-by: default avatarMoritz Fischer <mdf@kernel.org>

* tag 'fpga-for-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga:
  fpga: dfl: Allow Port to be linked to FME's DFL
  Documentation: fpga: dfl: add link address of feature id table
  fpga: dfl: check feature type before parse irq info
  fpga: fpga-region: fix kernel-doc formatting issues
  fpga: Use tab instead of space indentation
  fpga: fpga-mgr: fix kernel-doc warnings
  fpga: fix for coding style issues
  MAINTAINERS: Update linux-fpga repository location
parents 9c518db6 ae23f746

Documentation/fpga/dfl.rst

+5 −0
Original line number Diff line number Diff line
@@ -502,6 +502,11 @@ Developer only needs to provide a sub feature driver with matched feature id. 
FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)

could be a reference.



Please refer to below link to existing feature id table and guide for new feature

ids application.

https://github.com/OPAE/dfl-feature-id





Location of DFLs on a PCI Device

================================

The original method for finding a DFL on a PCI device assumed the start of the

MAINTAINERS

+1 −1
Original line number Diff line number Diff line
@@ -7732,7 +7732,7 @@ R: Tom Rix <trix@redhat.com> 
L:	linux-fpga@vger.kernel.org

S:	Maintained

Q:	http://patchwork.kernel.org/project/linux-fpga/list/

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga.git

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga.git

F:	Documentation/devicetree/bindings/fpga/

F:	Documentation/driver-api/fpga/

F:	Documentation/fpga/

drivers/fpga/dfl-pci.c

+9 −0
Original line number Diff line number Diff line
@@ -259,6 +259,15 @@ static int find_dfls_by_default(struct pci_dev *pcidev, 
			 */

			bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v);

			offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v);

			if (bar == FME_PORT_OFST_BAR_SKIP) {

				continue;

			} else if (bar >= PCI_STD_NUM_BARS) {

				dev_err(&pcidev->dev, "bad BAR %d for port %d\n",

					bar, i);

				ret = -EINVAL;

				break;

			}



			start = pci_resource_start(pcidev, bar) + offset;

			len = pci_resource_len(pcidev, bar) - offset;

drivers/fpga/dfl.c

+22 −16
Original line number Diff line number Diff line
@@ -940,9 +940,12 @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo, 
{

	void __iomem *base = binfo->ioaddr + ofst;

	unsigned int i, ibase, inr = 0;

	enum dfl_id_type type;

	int virq;

	u64 v;



	type = feature_dev_id_type(binfo->feature_dev);



	/*

	 * Ideally DFL framework should only read info from DFL header, but

	 * current version DFL only provides mmio resources information for
@@ -957,6 +960,7 @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo, 
	 * code will be added. But in order to be compatible to old version

	 * DFL, the driver may still fall back to these quirks.

	 */

	if (type == PORT_ID) {

		switch (fid) {

		case PORT_FEATURE_ID_UINT:

			v = readq(base + PORT_UINT_CAP);
@@ -968,11 +972,13 @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo, 
			ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v);

			inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v);

			break;

	case FME_FEATURE_ID_GLOBAL_ERR:

		}

	} else if (type == FME_ID) {

		if (fid == FME_FEATURE_ID_GLOBAL_ERR) {

			v = readq(base + FME_ERROR_CAP);

			ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v);

			inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v);

		break;

		}

	}



	if (!inr) {

drivers/fpga/dfl.h

+1 −0
Original line number Diff line number Diff line
@@ -89,6 +89,7 @@ 
#define FME_HDR_NEXT_AFU	NEXT_AFU

#define FME_HDR_CAP		0x30

#define FME_HDR_PORT_OFST(n)	(0x38 + ((n) * 0x8))

#define FME_PORT_OFST_BAR_SKIP	7

#define FME_HDR_BITSTREAM_ID	0x60

#define FME_HDR_BITSTREAM_MD	0x68