Commit baaaf55d authored by Ben Chuang's avatar Ben Chuang Committed by Ulf Hansson
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mmc: sdhci-pci-gli: Improve GL9763E L1 entry delay to increase battery life 



For GL9763E, although there is the best performance at the maximum delay.
Change the value to 20us in order to have better power consumption.
This change may reduce the maximum performance by 10%.

Signed-off-by: default avatarBen Chuang <ben.chuang@genesyslogic.com.tw>
Link: https://lore.kernel.org/r/20210407093816.8863-1-benchuanggli@gmail.com


Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 5e2ea2db

drivers/mmc/host/sdhci-pci-gli.c

+3 −3
Original line number Diff line number Diff line
@@ -90,7 +90,7 @@ 


#define PCIE_GLI_9763E_CFG2      0x8A4

#define   GLI_9763E_CFG2_L1DLY     GENMASK(28, 19)

#define   GLI_9763E_CFG2_L1DLY_MAX 0x3FF

#define   GLI_9763E_CFG2_L1DLY_MID 0x50



#define PCIE_GLI_9763E_MMC_CTRL  0x960

#define   GLI_9763E_HS400_SLOW     BIT(3)
@@ -810,8 +810,8 @@ static void gli_set_gl9763e(struct sdhci_pci_slot *slot) 


	pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value);

	value &= ~GLI_9763E_CFG2_L1DLY;

	/* set ASPM L1 entry delay to 260us */

	value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MAX);

	/* set ASPM L1 entry delay to 20us */

	value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID);

	pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value);



	pci_read_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, &value);