Commit ba515a58 authored by Kevin Wang's avatar Kevin Wang Committed by Alex Deucher
Browse files

drm/amdkfd: correct sienna_cichlid SDMA RLC register offset error 



1.correct KFD SDMA RLC queue register offset error.
(all sdma rlc register offset is base on SDMA0.RLC0_RLC0_RB_CNTL)
2.HQD_N_REGS (19+6+7+12)
  12: the 2 more resgisters than navi1x (SDMAx_RLCy_MIDCMD_DATA{9,10})

the patch also can be fixed NULL pointer issue when read
/sys/kernel/debug/kfd/hqds on sienna_cichlid chip.

Signed-off-by: default avatarKevin Wang <kevin1.wang@amd.com>
Reviewed-by: default avatarLikun Gao <Likun.Gao@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent 1a0b713c

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

+6 −6
Original line number Diff line number Diff line
@@ -156,16 +156,16 @@ static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev, 
				mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;

		break;

	case 1:

		sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0,

		sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,

				mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;

		break;

	case 2:

		sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA2, 0,

				mmSDMA2_RLC0_RB_CNTL) - mmSDMA2_RLC0_RB_CNTL;

		sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,

				mmSDMA2_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;

		break;

	case 3:

		sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA3, 0,

				mmSDMA3_RLC0_RB_CNTL) - mmSDMA2_RLC0_RB_CNTL;

		sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,

				mmSDMA3_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;

		break;

	}
@@ -450,7 +450,7 @@ static int hqd_sdma_dump_v10_3(struct kgd_dev *kgd, 
			engine_id, queue_id);

	uint32_t i = 0, reg;

#undef HQD_N_REGS

#define HQD_N_REGS (19+6+7+10)

#define HQD_N_REGS (19+6+7+12)



	*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);

	if (*dump == NULL)