Commit ba1dc7f2 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'char-misc-5.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc 

Pull char / misc driver updates from Greg KH:
 "Here is the big set of char/misc driver changes for 5.15-rc1.

  Lots of different driver subsystems are being updated in here,
  notably:

   - mhi subsystem update

   - fpga subsystem update

   - coresight/hwtracing subsystem update

   - interconnect subsystem update

   - nvmem subsystem update

   - parport drivers update

   - phy subsystem update

   - soundwire subsystem update

  and there are some other char/misc drivers being updated as well:

   - binder driver additions

   - new misc drivers

   - lkdtm driver updates

   - mei driver updates

   - sram driver updates

   - other minor driver updates.

  Note, there are no habanalabs driver updates in this pull request,
  that will probably come later before -rc1 is out in a different
  request.

  All of these have been in linux-next for a while with no reported
  problems"

* tag 'char-misc-5.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (169 commits)
  Revert "bus: mhi: Add inbound buffers allocation flag"
  misc/pvpanic: fix set driver data
  VMCI: fix NULL pointer dereference when unmapping queue pair
  char: mware: fix returnvar.cocci warnings
  parport: remove non-zero check on count
  soundwire: cadence: do not extend reset delay
  soundwire: intel: conditionally exit clock stop mode on system suspend
  soundwire: intel: skip suspend/resume/wake when link was not started
  soundwire: intel: fix potential race condition during power down
  phy: qcom-qmp: Add support for SM6115 UFS phy
  dt-bindings: phy: qcom,qmp: Add SM6115 UFS PHY bindings
  phy: qmp: Provide unique clock names for DP clocks
  lkdtm: remove IDE_CORE_CP crashpoint
  lkdtm: replace SCSI_DISPATCH_CMD with SCSI_QUEUE_RQ
  coresight: Replace deprecated CPU-hotplug functions.
  Documentation: coresight: Add documentation for CoreSight config
  coresight: syscfg: Add initial configfs support
  coresight: config: Add preloaded configurations
  coresight: etm4x: Add complex configuration handlers to etmv4
  coresight: etm-perf: Update to activate selected configuration
  ...
parents 9e9fb765 0dc3ad3f

Documentation/ABI/testing/sysfs-driver-ge-achc

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What:		/sys/bus/spi/<dev>/update_firmware

Date:		Jul 2021

Contact:	sebastian.reichel@collabora.com

Description:	Write 1 to this file to update the ACHC microcontroller

		firmware via the EzPort interface. For this the kernel

		will load "achc.bin" via the firmware API (so usually

		from /lib/firmware). The write will block until the FW

		has either been flashed successfully or an error occured.



What:		/sys/bus/spi/<dev>/reset

Date:		Jul 2021

Contact:	sebastian.reichel@collabora.com

Description:	This file represents the microcontroller's reset line.

                1 means the reset line is asserted, 0 means it's not

		asserted. The file is read and writable.

Documentation/admin-guide/binderfs.rst

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@@ -72,3 +72,16 @@ that the `rm() <rm_>`_ tool can be used to delete them. Note that the 
``binder-control`` device cannot be deleted since this would make the binderfs

instance unusable.  The ``binder-control`` device will be deleted when the

binderfs instance is unmounted and all references to it have been dropped.



Binder features

---------------



Assuming an instance of binderfs has been mounted at ``/dev/binderfs``, the

features supported by the binder driver can be located under

``/dev/binderfs/features/``. The presence of individual files can be tested

to determine whether a particular feature is supported by the driver.



Example::



        cat /dev/binderfs/features/oneway_spam_detection

        1

Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt

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-----------------------------------------------------------------

Device Tree Bindings for the Xilinx Zynq MPSoC Firmware Interface

-----------------------------------------------------------------



The zynqmp-firmware node describes the interface to platform firmware.

ZynqMP has an interface to communicate with secure firmware. Firmware

driver provides an interface to firmware APIs. Interface APIs can be

used by any driver to communicate to PMUFW(Platform Management Unit).

These requests include clock management, pin control, device control,

power management service, FPGA service and other platform management

services.



Required properties:

 - compatible:	Must contain any of below:

		"xlnx,zynqmp-firmware" for Zynq Ultrascale+ MPSoC

		"xlnx,versal-firmware" for Versal

 - method:	The method of calling the PM-API firmware layer.

		Permitted values are:

		  - "smc" : SMC #0, following the SMCCC

		  - "hvc" : HVC #0, following the SMCCC



-------

Example

-------



Zynq Ultrascale+ MPSoC

----------------------

firmware {

	zynqmp_firmware: zynqmp-firmware {

		compatible = "xlnx,zynqmp-firmware";

		method = "smc";

		...

	};

};



Versal

------

firmware {

	versal_firmware: versal-firmware {

		compatible = "xlnx,versal-firmware";

		method = "smc";

		...

	};

};

Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Xilinx firmware driver



maintainers:

  - Nava kishore Manne <nava.manne@xilinx.com>



description: The zynqmp-firmware node describes the interface to platform

  firmware. ZynqMP has an interface to communicate with secure firmware.

  Firmware driver provides an interface to firmware APIs. Interface APIs

  can be used by any driver to communicate to PMUFW(Platform Management Unit).

  These requests include clock management, pin control, device control,

  power management service, FPGA service and other platform management

  services.



properties:

  compatible:

    oneOf:

      - description: For implementations complying for Zynq Ultrascale+ MPSoC.

        const: xlnx,zynqmp-firmware



      - description: For implementations complying for Versal.

        const: xlnx,versal-firmware



  method:

    description: |

                 The method of calling the PM-API firmware layer.

                 Permitted values are.

                 - "smc" : SMC #0, following the SMCCC

                 - "hvc" : HVC #0, following the SMCCC



    $ref: /schemas/types.yaml#/definitions/string-array

    enum:

      - smc

      - hvc



  versal_fpga:

    $ref: /schemas/fpga/xlnx,versal-fpga.yaml#

    description: Compatible of the FPGA device.

    type: object



  zynqmp-aes:

    $ref: /schemas/crypto/xlnx,zynqmp-aes.yaml#

    description: The ZynqMP AES-GCM hardened cryptographic accelerator is

      used to encrypt or decrypt the data with provided key and initialization

      vector.

    type: object



  clock-controller:

    $ref: /schemas/clock/xlnx,versal-clk.yaml#

    description: The clock controller is a hardware block of Xilinx versal

      clock tree. It reads required input clock frequencies from the devicetree

      and acts as clock provider for all clock consumers of PS clocks.list of

      clock specifiers which are external input clocks to the given clock

      controller.

    type: object



required:

  - compatible



additionalProperties: false



examples:

  - |

    versal-firmware {

      compatible = "xlnx,versal-firmware";

      method = "smc";



      versal_fpga: versal_fpga {

        compatible = "xlnx,versal-fpga";

      };



      xlnx_aes: zynqmp-aes {

        compatible = "xlnx,zynqmp-aes";

      };



      versal_clk: clock-controller {

        #clock-cells = <1>;

        compatible = "xlnx,versal-clk";

        clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;

        clock-names = "ref", "alt_ref", "pl_alt_ref";

      };

    };



...

Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/fpga/xlnx,versal-fpga.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Xilinx Versal FPGA driver.



maintainers:

  - Nava kishore Manne <nava.manne@xilinx.com>



description: |

  Device Tree Versal FPGA bindings for the Versal SoC, controlled

  using firmware interface.



properties:

  compatible:

    items:

      - enum:

          - xlnx,versal-fpga



required:

  - compatible



additionalProperties: false



examples:

  - |

    versal_fpga: versal_fpga {

         compatible = "xlnx,versal-fpga";

    };



...