Commit ba1af6e2 authored by Anup Patel's avatar Anup Patel Committed by Anup Patel
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KVM: riscv: selftests: Fix ISA_EXT register handling in get-reg-list 



Same set of ISA_EXT registers are not present on all host because
ISA_EXT registers are visible to the KVM user space based on the
ISA extensions available on the host. Also, disabling an ISA
extension using corresponding ISA_EXT register does not affect
the visibility of the ISA_EXT register itself.

Based on the above, we should filter-out all ISA_EXT registers.

Fixes: 47706939 ("KVM: riscv: selftests: Add get-reg-list test")
Signed-off-by: default avatarAnup Patel <apatel@ventanamicro.com>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Signed-off-by: default avatarAnup Patel <anup@brainfault.org>
parent 17f71a2a

tools/testing/selftests/kvm/riscv/get-reg-list.c

+21 −14
Original line number Diff line number Diff line
@@ -14,17 +14,33 @@ 


bool filter_reg(__u64 reg)

{

	switch (reg & ~REG_MASK) {

	/*

	 * Some ISA extensions are optional and not present on all host,

	 * but they can't be disabled through ISA_EXT registers when present.

	 * So, to make life easy, just filtering out these kind of registers.

	 * Same set of ISA_EXT registers are not present on all host because

	 * ISA_EXT registers are visible to the KVM user space based on the

	 * ISA extensions available on the host. Also, disabling an ISA

	 * extension using corresponding ISA_EXT register does not affect

	 * the visibility of the ISA_EXT register itself.

	 *

	 * Based on above, we should filter-out all ISA_EXT registers.

	 */

	switch (reg & ~REG_MASK) {

	case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_A:

	case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_C:

	case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_D:

	case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_F:

	case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_H:

	case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_I:

	case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_M:

	case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVPBMT:

	case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSTC:

	case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVINVAL:

	case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHINTPAUSE:

	case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOM:

	case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOZ:

	case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBB:

	case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA:

	case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_V:

	case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVNAPOT:

	case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBA:

	case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBS:

	case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICNTR:
@@ -50,12 +66,7 @@ static inline bool vcpu_has_ext(struct kvm_vcpu *vcpu, int ext) 
	unsigned long value;



	ret = __vcpu_get_reg(vcpu, RISCV_ISA_EXT_REG(ext), &value);

	if (ret) {

		printf("Failed to get ext %d", ext);

		return false;

	}



	return !!value;

	return (ret) ? false : !!value;

}



void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_reg_list *c)
@@ -506,10 +517,6 @@ static __u64 base_regs[] = { 
	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(time),

	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(compare),

	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(state),

	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_A,

	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_C,

	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_I,

	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_M,

	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_V01,

	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_TIME,

	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_IPI,