Commit ba1a98e8 authored by Vincenzo Frascino's avatar Vincenzo Frascino Committed by Will Deacon
Browse files

arm64: mte: Bitfield definitions for Asymm MTE 



Add Asymmetric Memory Tagging Extension bitfield definitions.

Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarVincenzo Frascino <vincenzo.frascino@arm.com>
Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20211006154751.4463-3-vincenzo.frascino@arm.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent f5627ec1

arch/arm64/include/asm/sysreg.h

+3 −0
Original line number Diff line number Diff line
@@ -621,6 +621,7 @@ 
#define SCTLR_ELx_TCF_NONE	(UL(0x0) << SCTLR_ELx_TCF_SHIFT)

#define SCTLR_ELx_TCF_SYNC	(UL(0x1) << SCTLR_ELx_TCF_SHIFT)

#define SCTLR_ELx_TCF_ASYNC	(UL(0x2) << SCTLR_ELx_TCF_SHIFT)

#define SCTLR_ELx_TCF_ASYMM	(UL(0x3) << SCTLR_ELx_TCF_SHIFT)

#define SCTLR_ELx_TCF_MASK	(UL(0x3) << SCTLR_ELx_TCF_SHIFT)



#define SCTLR_ELx_ENIA_SHIFT	31
@@ -666,6 +667,7 @@ 
#define SCTLR_EL1_TCF0_NONE	(UL(0x0) << SCTLR_EL1_TCF0_SHIFT)

#define SCTLR_EL1_TCF0_SYNC	(UL(0x1) << SCTLR_EL1_TCF0_SHIFT)

#define SCTLR_EL1_TCF0_ASYNC	(UL(0x2) << SCTLR_EL1_TCF0_SHIFT)

#define SCTLR_EL1_TCF0_ASYMM	(UL(0x3) << SCTLR_EL1_TCF0_SHIFT)

#define SCTLR_EL1_TCF0_MASK	(UL(0x3) << SCTLR_EL1_TCF0_SHIFT)



#define SCTLR_EL1_BT1		(BIT(36))
@@ -807,6 +809,7 @@ 
#define ID_AA64PFR1_MTE_NI		0x0

#define ID_AA64PFR1_MTE_EL0		0x1

#define ID_AA64PFR1_MTE			0x2

#define ID_AA64PFR1_MTE_ASYMM		0x3



/* id_aa64zfr0 */

#define ID_AA64ZFR0_F64MM_SHIFT		56