Commit ba136b5e authored by Fabien Parent's avatar Fabien Parent Committed by Matthias Brugger
Browse files

soc: mediatek: pwrap: add mt8365 SoC support 



Add PMIC Wrap support for MT8365 SoC.

Signed-off-by: default avatarFabien Parent <fparent@baylibre.com>
Signed-off-by: default avatarFadwa CHIBY <fchiby@baylibre.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221031093401.22916-4-fchiby@baylibre.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 55924157

drivers/soc/mediatek/mtk-pmic-wrap.c

+78 −0
Original line number Diff line number Diff line
@@ -983,6 +983,68 @@ static int mt8195_regs[] = { 
	[PWRAP_WACS2_RDATA] =		0x8A8,

};



static int mt8365_regs[] = {

	[PWRAP_MUX_SEL] =		0x0,

	[PWRAP_WRAP_EN] =		0x4,

	[PWRAP_DIO_EN] =		0x8,

	[PWRAP_CSHEXT_WRITE] =		0x24,

	[PWRAP_CSHEXT_READ] =		0x28,

	[PWRAP_STAUPD_PRD] =		0x3c,

	[PWRAP_STAUPD_GRPEN] =		0x40,

	[PWRAP_STAUPD_MAN_TRIG] =	0x58,

	[PWRAP_STAUPD_STA] =		0x5c,

	[PWRAP_WRAP_STA] =		0x60,

	[PWRAP_HARB_INIT] =		0x64,

	[PWRAP_HARB_HPRIO] =		0x68,

	[PWRAP_HIPRIO_ARB_EN] =		0x6c,

	[PWRAP_HARB_STA0] =		0x70,

	[PWRAP_HARB_STA1] =		0x74,

	[PWRAP_MAN_EN] =		0x7c,

	[PWRAP_MAN_CMD] =		0x80,

	[PWRAP_MAN_RDATA] =		0x84,

	[PWRAP_MAN_VLDCLR] =		0x88,

	[PWRAP_WACS0_EN] =		0x8c,

	[PWRAP_INIT_DONE0] =		0x90,

	[PWRAP_WACS0_CMD] =		0xc00,

	[PWRAP_WACS0_RDATA] =		0xc04,

	[PWRAP_WACS0_VLDCLR] =		0xc08,

	[PWRAP_WACS1_EN] =		0x94,

	[PWRAP_INIT_DONE1] =		0x98,

	[PWRAP_WACS2_EN] =		0x9c,

	[PWRAP_INIT_DONE2] =		0xa0,

	[PWRAP_WACS2_CMD] =		0xc20,

	[PWRAP_WACS2_RDATA] =		0xc24,

	[PWRAP_WACS2_VLDCLR] =		0xc28,

	[PWRAP_INT_EN] =		0xb4,

	[PWRAP_INT_FLG_RAW] =		0xb8,

	[PWRAP_INT_FLG] =		0xbc,

	[PWRAP_INT_CLR] =		0xc0,

	[PWRAP_SIG_ADR] =		0xd4,

	[PWRAP_SIG_MODE] =		0xd8,

	[PWRAP_SIG_VALUE] =		0xdc,

	[PWRAP_SIG_ERRVAL] =		0xe0,

	[PWRAP_CRC_EN] =		0xe4,

	[PWRAP_TIMER_EN] =		0xe8,

	[PWRAP_TIMER_STA] =		0xec,

	[PWRAP_WDT_UNIT] =		0xf0,

	[PWRAP_WDT_SRC_EN] =		0xf4,

	[PWRAP_WDT_FLG] =		0xfc,

	[PWRAP_DEBUG_INT_SEL] =		0x104,

	[PWRAP_CIPHER_KEY_SEL] =	0x1c4,

	[PWRAP_CIPHER_IV_SEL] =		0x1c8,

	[PWRAP_CIPHER_RDY] =		0x1d0,

	[PWRAP_CIPHER_MODE] =		0x1d4,

	[PWRAP_CIPHER_SWRST] =		0x1d8,

	[PWRAP_DCM_EN] =		0x1dc,

	[PWRAP_DCM_DBC_PRD] =		0x1e0,

	[PWRAP_EINT_STA0_ADR] =		0x44,

	[PWRAP_EINT_STA1_ADR] =		0x48,

	[PWRAP_INT1_EN] =		0xc4,

	[PWRAP_INT1_FLG] =		0xcc,

	[PWRAP_INT1_CLR] =		0xd0,

	[PWRAP_WDT_SRC_EN_1] =		0xf8,

};



static int mt8516_regs[] = {

	[PWRAP_MUX_SEL] =		0x0,

	[PWRAP_WRAP_EN] =		0x4,
@@ -1139,6 +1201,7 @@ enum pwrap_type { 
	PWRAP_MT8183,

	PWRAP_MT8186,

	PWRAP_MT8195,

	PWRAP_MT8365,

	PWRAP_MT8516,

};
@@ -1598,6 +1661,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) 
	case PWRAP_MT6797:

	case PWRAP_MT8173:

	case PWRAP_MT8186:

	case PWRAP_MT8365:

	case PWRAP_MT8516:

		pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);

		break;
@@ -2106,6 +2170,19 @@ static struct pmic_wrapper_type pwrap_mt8195 = { 
	.init_soc_specific = NULL,

};



static const struct pmic_wrapper_type pwrap_mt8365 = {

	.regs = mt8365_regs,

	.type = PWRAP_MT8365,

	.arb_en_all = 0x3ffff,

	.int_en_all = 0x7f1fffff,

	.int1_en_all = 0x0,

	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,

	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,

	.caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_WDT_SRC1,

	.init_reg_clock = pwrap_common_init_reg_clock,

	.init_soc_specific = NULL,

};



static struct pmic_wrapper_type pwrap_mt8516 = {

	.regs = mt8516_regs,

	.type = PWRAP_MT8516,
@@ -2143,6 +2220,7 @@ static const struct of_device_id of_pwrap_match_tbl[] = { 
	{ .compatible = "mediatek,mt8183-pwrap", .data = &pwrap_mt8183 },

	{ .compatible = "mediatek,mt8186-pwrap", .data = &pwrap_mt8186 },

	{ .compatible = "mediatek,mt8195-pwrap", .data = &pwrap_mt8195 },

	{ .compatible = "mediatek,mt8365-pwrap", .data = &pwrap_mt8365 },

	{ .compatible = "mediatek,mt8516-pwrap", .data = &pwrap_mt8516 },

	{ /* sentinel */ }

};