Commit ba0ae9ac authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2020-03-06' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Weekly fixes round, looks like a few people woke up, got a bunch of
  fixes across the drivers. Bit bigger than I'd like but they all seem
  fine and hopefully it quiets down now.

  sun4i, kirin, mediatek and exynos on the ARM side. virtio-gpu and core
  have some mmap fixes, and there is a dma-buf leak. one ttm fence leak
  is also fixed.

  Otherwise it's mostly amdgpu and i915.

  One of the i915 fixes is for a very long latency I was seeing (using
  latencytop) running gnome-shell locally when using firefox and eating
  nearly all my RAM, it really helps with desktop responsiveness esp
  when firefox is chewing a lot.

  dma-buf:
   - fix memory leak

  core:
   - shmem object mmap fix.

  ttm:
   - Fix fence leak in ttm_buffer_object_transfer().

  amdgpu:
   - Gfx reset fix for gfx9, 10
   - Fix for gfx10
   - DP MST fix
   - DCC fix
   - Renoir power fixes
   - Navi power fix

  i915:
   - Break up long lists of object reclaim with cond_resched()
   - PSR probe fix
   - TGL workarounds
   - Selftest return value fix
   - Drop timeline mutex while waiting for retirement
   - Wait for OA configuration completion before writes to OA buffer

  virtio:
   - Fix resource id creation race in virtio.
   - mmap fixes

  sun4i:
   - Fixes for sun4i VI layer format support.

  kirin:
   - kirin: Revert "Fix for hikey620 display offset problem"

  exynos:
   - fix a kernel oops problem in case that driver is loaded as module.
   - fix a regulator warning issue when I2C DDC adapter cannot be gathered.
   - print out an error message only in error case excepting -EPROBE_DEFER.

  mediatek:
   - overlay, cursor and gce fixes"
`

* tag 'drm-fixes-2020-03-06' of git://anongit.freedesktop.org/drm/drm: (38 commits)
  drm/amdgpu/display: navi1x copy dcn watermark clock settings to smu resume from s3 (v2)
  drm/amd/powerplay: map mclk to fclk for COMBINATIONAL_BYPASS case
  drm/amd/powerplay: fix pre-check condition for setting clock range
  drm/amd/display: fix dcc swath size calculations on dcn1
  drm/amd/display: Clear link settings on MST disable connector
  drm/amdgpu: disable 3D pipe 1 on Navi1x
  drm/amdgpu: clean wptr on wb when gpu recovery
  drm: kirin: Revert "Fix for hikey620 display offset problem"
  drm/i915/gt: Drop the timeline->mutex as we wait for retirement
  drm/i915/perf: Reintroduce wait on OA configuration completion
  drm/sun4i: Fix DE2 VI layer format support
  drm/sun4i: Add separate DE3 VI layer formats
  drm/sun4i: de2/de3: Remove unsupported VI layer formats
  drm/i915/selftests: Fix return in assert_mmap_offset()
  drm/i915: Protect i915_request_await_start from early waits
  drm/i915/tgl: Add Wa_1608008084
  drm/i915/tgl: Add Wa_22010178259:tgl
  drm/i915: Program MBUS with rmw during initialization
  drm/i915/psr: Force PSR probe only after full initialization
  drm/i915/gem: Break up long lists of object reclaim
  ...
parents 9f65ed5f 2ac4853e

drivers/dma-buf/dma-buf.c

+1 −0
Original line number Diff line number Diff line
@@ -108,6 +108,7 @@ static int dma_buf_release(struct inode *inode, struct file *file) 
		dma_resv_fini(dmabuf->resv);



	module_put(dmabuf->owner);

	kfree(dmabuf->name);

	kfree(dmabuf);

	return 0;

}

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+52 −46
Original line number Diff line number Diff line
@@ -52,7 +52,7 @@ 
 * 1. Primary ring

 * 2. Async ring

 */

#define GFX10_NUM_GFX_RINGS	2

#define GFX10_NUM_GFX_RINGS_NV1X	1

#define GFX10_MEC_HPD_SIZE	2048



#define F32_CE_PROGRAM_RAM_SIZE		65536
@@ -1304,7 +1304,7 @@ static int gfx_v10_0_sw_init(void *handle) 
	case CHIP_NAVI14:

	case CHIP_NAVI12:

		adev->gfx.me.num_me = 1;

		adev->gfx.me.num_pipe_per_me = 2;

		adev->gfx.me.num_pipe_per_me = 1;

		adev->gfx.me.num_queue_per_pipe = 1;

		adev->gfx.mec.num_mec = 2;

		adev->gfx.mec.num_pipe_per_mec = 4;
@@ -2710,6 +2710,8 @@ static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 
	amdgpu_ring_commit(ring);



	/* submit cs packet to copy state 0 to next available state */

	if (adev->gfx.num_gfx_rings > 1) {

		/* maximum supported gfx ring is 2 */

		ring = &adev->gfx.gfx_ring[1];

		r = amdgpu_ring_alloc(ring, 2);

		if (r) {
@@ -2721,7 +2723,7 @@ static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 
		amdgpu_ring_write(ring, 0);



		amdgpu_ring_commit(ring);



	}

	return 0;

}
@@ -2818,8 +2820,10 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 
	mutex_unlock(&adev->srbm_mutex);



	/* Init gfx ring 1 for pipe 1 */

	if (adev->gfx.num_gfx_rings > 1) {

		mutex_lock(&adev->srbm_mutex);

		gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);

		/* maximum supported gfx ring is 2 */

		ring = &adev->gfx.gfx_ring[1];

		rb_bufsz = order_base_2(ring->ring_size / 8);

		tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
@@ -2850,7 +2854,7 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 


		gfx_v10_0_cp_gfx_set_doorbell(adev, ring);

		mutex_unlock(&adev->srbm_mutex);



	}

	/* Switch to pipe 0 */

	mutex_lock(&adev->srbm_mutex);

	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
@@ -3513,6 +3517,7 @@ static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 


		/* reset ring buffer */

		ring->wptr = 0;

		atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);

		amdgpu_ring_clear_ring(ring);

	} else {

		amdgpu_ring_clear_ring(ring);
@@ -3966,7 +3971,8 @@ static int gfx_v10_0_early_init(void *handle) 
{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS;

	adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;



	adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;



	gfx_v10_0_set_kiq_pm4_funcs(adev);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+1 −0
Original line number Diff line number Diff line
@@ -3663,6 +3663,7 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) 


		/* reset ring buffer */

		ring->wptr = 0;

		atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);

		amdgpu_ring_clear_ring(ring);

	} else {

		amdgpu_ring_clear_ring(ring);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+69 −0
Original line number Diff line number Diff line
@@ -1422,6 +1422,73 @@ static void s3_handle_mst(struct drm_device *dev, bool suspend) 
		drm_kms_helper_hotplug_event(dev);

}



static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)

{

	struct smu_context *smu = &adev->smu;

	int ret = 0;



	if (!is_support_sw_smu(adev))

		return 0;



	/* This interface is for dGPU Navi1x.Linux dc-pplib interface depends

	 * on window driver dc implementation.

	 * For Navi1x, clock settings of dcn watermarks are fixed. the settings

	 * should be passed to smu during boot up and resume from s3.

	 * boot up: dc calculate dcn watermark clock settings within dc_create,

	 * dcn20_resource_construct

	 * then call pplib functions below to pass the settings to smu:

	 * smu_set_watermarks_for_clock_ranges

	 * smu_set_watermarks_table

	 * navi10_set_watermarks_table

	 * smu_write_watermarks_table

	 *

	 * For Renoir, clock settings of dcn watermark are also fixed values.

	 * dc has implemented different flow for window driver:

	 * dc_hardware_init / dc_set_power_state

	 * dcn10_init_hw

	 * notify_wm_ranges

	 * set_wm_ranges

	 * -- Linux

	 * smu_set_watermarks_for_clock_ranges

	 * renoir_set_watermarks_table

	 * smu_write_watermarks_table

	 *

	 * For Linux,

	 * dc_hardware_init -> amdgpu_dm_init

	 * dc_set_power_state --> dm_resume

	 *

	 * therefore, this function apply to navi10/12/14 but not Renoir

	 * *

	 */

	switch(adev->asic_type) {

	case CHIP_NAVI10:

	case CHIP_NAVI14:

	case CHIP_NAVI12:

		break;

	default:

		return 0;

	}



	mutex_lock(&smu->mutex);



	/* pass data to smu controller */

	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&

			!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {

		ret = smu_write_watermarks_table(smu);



		if (ret) {

			mutex_unlock(&smu->mutex);

			DRM_ERROR("Failed to update WMTABLE!\n");

			return ret;

		}

		smu->watermarks_bitmap |= WATERMARKS_LOADED;

	}



	mutex_unlock(&smu->mutex);



	return 0;

}



/**

 * dm_hw_init() - Initialize DC device

 * @handle: The base driver device containing the amdgpu_dm device.
@@ -1700,6 +1767,8 @@ static int dm_resume(void *handle) 


	amdgpu_dm_irq_resume_late(adev);



	amdgpu_dm_smu_write_watermarks_table(adev);



	return 0;

}

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

+1 −0
Original line number Diff line number Diff line
@@ -451,6 +451,7 @@ static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, 
					   aconnector->dc_sink);

		dc_sink_release(aconnector->dc_sink);

		aconnector->dc_sink = NULL;

		aconnector->dc_link->cur_link_settings.lane_count = 0;

	}



	drm_connector_unregister(connector);