Commit b961aa75 authored by Vitaly Kuznetsov's avatar Vitaly Kuznetsov Committed by Paolo Bonzini
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x86/hyperv: Add HV_EXPOSE_INVARIANT_TSC define 



Avoid open coding BIT(0) of HV_X64_MSR_TSC_INVARIANT_CONTROL by adding
a dedicated define. While there's only one user at this moment, the
upcoming KVM implementation of Hyper-V Invariant TSC feature will need
to use it as well.

Reviewed-by: default avatarMichael Kelley <mikelley@microsoft.com>
Signed-off-by: default avatarVitaly Kuznetsov <vkuznets@redhat.com>
Reviewed-by: default avatarSean Christopherson <seanjc@google.com>
Message-Id: <20221013095849.705943-2-vkuznets@redhat.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent dfe0ecc6

arch/x86/include/asm/hyperv-tlfs.h

+3 −0
Original line number Diff line number Diff line
@@ -255,6 +255,9 @@ enum hv_isolation_type { 
/* TSC invariant control */

#define HV_X64_MSR_TSC_INVARIANT_CONTROL	0x40000118



/* HV_X64_MSR_TSC_INVARIANT_CONTROL bits */

#define HV_EXPOSE_INVARIANT_TSC		BIT_ULL(0)



/* Register name aliases for temporary compatibility */

#define HV_X64_MSR_STIMER0_COUNT	HV_REGISTER_STIMER0_COUNT

#define HV_X64_MSR_STIMER0_CONFIG	HV_REGISTER_STIMER0_CONFIG

arch/x86/kernel/cpu/mshyperv.c

+1 −1
Original line number Diff line number Diff line
@@ -388,7 +388,7 @@ static void __init ms_hyperv_init_platform(void) 
		 * setting of this MSR bit should happen before init_intel()

		 * is called.

		 */

		wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, 0x1);

		wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, HV_EXPOSE_INVARIANT_TSC);

		setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);

	}