Unverified Commit b903f9c5 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'memory-controller-drv-5.18' of... 

Merge tag 'memory-controller-drv-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers

Memory controller drivers for v5.18

1. Minor improvements: Mediatek SMI, Freescale/NXP IFC, Tegra20 and
   Tegra30.
2. Convert Freescale/NXP IFC bindings to dtschema.
3. Convert LPDDR bindings to dtschema.
4. Adjust revision ID property in LPDDR2 bindings to match LPDDR3
   bindings.

* tag 'memory-controller-drv-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  memory: Update of_memory lpddr2 revision-id binding
  dt-bindings: memory: lpddr2: Adjust revision ID property to match lpddr3
  memory: of: parse max-freq property
  dt-bindings: memory: lpddr3: deprecate passing timings frequency as unit address
  dt-bindings: memory: lpddr3: deprecate manufacturer ID
  dt-bindings: memory: lpddr3: adjust IO width to spec
  dt-bindings: memory: lpddr3: convert to dtschema
  dt-bindings: memory: lpddr3-timings: convert to dtschema
  dt-bindings: memory: lpddr2-timings: convert to dtschema
  memory: brcmstb_dpfe: fix typo in a comment
  memory: fsl_ifc: populate child devices without relying on simple-bus
  dt-bindings: memory: fsl: convert ifc binding to yaml schema
  memory: mtk-smi: Use ARRAY_SIZE to define MTK_SMI_CLK_NR_MAX

Link: https://lore.kernel.org/r/20220228164313.52931-1-krzysztof.kozlowski@canonical.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 254a1864 a06bf59d

Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: LPDDR2 SDRAM AC timing parameters for a given speed-bin



maintainers:

  - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>



properties:

  compatible:

    const: jedec,lpddr2-timings



  max-freq:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Maximum DDR clock frequency for the speed-bin, in Hz.



  min-freq:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Minimum DDR clock frequency for the speed-bin, in Hz.



  tCKESR:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      CKE minimum pulse width during SELF REFRESH (low pulse width during

      SELF REFRESH) in pico seconds.



  tDQSCK-max:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      DQS output data access time from CK_t/CK_c in pico seconds.



  tDQSCK-max-derated:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      DQS output data access time from CK_t/CK_c, temperature de-rated, in pico

      seconds.



  tFAW:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Four-bank activate window in pico seconds.



  tRAS-max-ns:

    description: |

      Row active time in nano seconds.



  tRAS-min:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Row active time in pico seconds.



  tRCD:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      RAS-to-CAS delay in pico seconds.



  tRPab:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Row precharge time (all banks) in pico seconds.



  tRRD:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Active bank A to active bank B in pico seconds.



  tRTP:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Internal READ to PRECHARGE command delay in pico seconds.



  tWR:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      WRITE recovery time in pico seconds.



  tWTR:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Internal WRITE-to-READ command delay in pico seconds.



  tXP:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Exit power-down to next valid command delay in pico seconds.



  tZQCL:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Long calibration time in pico seconds.



  tZQCS:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Short calibration time in pico seconds.



  tZQinit:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Initialization calibration time in pico seconds.



required:

  - compatible

  - min-freq

  - max-freq



additionalProperties: false



examples:

  - |

    timings {

        compatible = "jedec,lpddr2-timings";

        min-freq = <10000000>;

        max-freq = <400000000>;

        tCKESR = <15000>;

        tDQSCK-max = <5500>;

        tFAW = <50000>;

        tRAS-max-ns = <70000>;

        tRAS-min = <42000>;

        tRPab = <21000>;

        tRCD = <18000>;

        tRRD = <10000>;

        tRTP = <7500>;

        tWR = <15000>;

        tWTR = <7500>;

        tXP = <7500>;

        tZQCL = <360000>;

        tZQCS = <90000>;

        tZQinit = <1000000>;

    };

Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml

+17 −6
Original line number Original line Diff line number Diff line
@@ -30,12 +30,26 @@ properties: 
    maximum: 255

    maximum: 255

    description: |

    description: |

      Revision 1 value of SDRAM chip. Obtained from device datasheet.

      Revision 1 value of SDRAM chip. Obtained from device datasheet.

      Property is deprecated, use revision-id instead.

    deprecated: true





  revision-id2:

  revision-id2:

    $ref: /schemas/types.yaml#/definitions/uint32

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 255

    maximum: 255

    description: |

    description: |

      Revision 2 value of SDRAM chip. Obtained from device datasheet.

      Revision 2 value of SDRAM chip. Obtained from device datasheet.

      Property is deprecated, use revision-id instead.

    deprecated: true



  revision-id:

    $ref: /schemas/types.yaml#/definitions/uint32-array

    description: |

      Revision IDs read from Mode Register 6 and 7. One byte per uint32 cell (i.e. <MR6 MR7>).

    minItems: 2

    maxItems: 2

    items:

      minimum: 0

      maximum: 255





  density:

  density:

    $ref: /schemas/types.yaml#/definitions/uint32

    $ref: /schemas/types.yaml#/definitions/uint32
@@ -142,14 +156,12 @@ properties: 




patternProperties:

patternProperties:

  "^lpddr2-timings":

  "^lpddr2-timings":

    type: object

    $ref: jedec,lpddr2-timings.yaml

    description: |

    description: |

      The lpddr2 node may have one or more child nodes of type "lpddr2-timings".

      The lpddr2 node may have one or more child nodes of type "lpddr2-timings".

      "lpddr2-timings" provides AC timing parameters of the device for

      "lpddr2-timings" provides AC timing parameters of the device for

      a given speed-bin. The user may provide the timings for as many

      a given speed-bin. The user may provide the timings for as many

      speed-bins as is required. Please see Documentation/devicetree/

      speed-bins as is required.

      bindings/memory-controllers/ddr/lpddr2-timings.txt for more information

      on "lpddr2-timings".





required:

required:

  - compatible

  - compatible
@@ -164,8 +176,7 @@ examples: 
        compatible = "elpida,ECB240ABACN", "jedec,lpddr2-s4";

        compatible = "elpida,ECB240ABACN", "jedec,lpddr2-s4";

        density = <2048>;

        density = <2048>;

        io-width = <32>;

        io-width = <32>;

        revision-id1 = <1>;

        revision-id = <1 0>;

        revision-id2 = <0>;





        tRPab-min-tck = <3>;

        tRPab-min-tck = <3>;

        tRCD-min-tck = <3>;

        tRCD-min-tck = <3>;

Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: LPDDR3 SDRAM AC timing parameters for a given speed-bin



maintainers:

  - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>



properties:

  compatible:

    const: jedec,lpddr3-timings



  reg:

    maxItems: 1

    description: |

      Maximum DDR clock frequency for the speed-bin, in Hz.

      Property is deprecated, use max-freq.

    deprecated: true



  max-freq:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Maximum DDR clock frequency for the speed-bin, in Hz.



  min-freq:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Minimum DDR clock frequency for the speed-bin, in Hz.



  tCKE:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      CKE minimum pulse width (HIGH and LOW pulse width) in pico seconds.



  tCKESR:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      CKE minimum pulse width during SELF REFRESH (low pulse width during

      SELF REFRESH) in pico seconds.



  tFAW:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Four-bank activate window in pico seconds.



  tMRD:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Mode register set command delay in pico seconds.



  tR2R-C2C:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Additional READ-to-READ delay in chip-to-chip cases in pico seconds.



  tRAS:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Row active time in pico seconds.



  tRC:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      ACTIVATE-to-ACTIVATE command period in pico seconds.



  tRCD:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      RAS-to-CAS delay in pico seconds.



  tRFC:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Refresh Cycle time in pico seconds.



  tRPab:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Row precharge time (all banks) in pico seconds.



  tRPpb:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Row precharge time (single banks) in pico seconds.



  tRRD:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Active bank A to active bank B in pico seconds.



  tRTP:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Internal READ to PRECHARGE command delay in pico seconds.



  tW2W-C2C:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Additional WRITE-to-WRITE delay in chip-to-chip cases in pico seconds.



  tWR:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      WRITE recovery time in pico seconds.



  tWTR:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Internal WRITE-to-READ command delay in pico seconds.



  tXP:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Exit power-down to next valid command delay in pico seconds.



  tXSR:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      SELF REFRESH exit to next valid command delay in pico seconds.



required:

  - compatible

  - min-freq

  - max-freq



additionalProperties: false



examples:

  - |

    lpddr3 {

        timings {

            compatible = "jedec,lpddr3-timings";

            max-freq = <800000000>;

            min-freq = <100000000>;

            tCKE = <3750>;

            tCKESR = <3750>;

            tFAW = <25000>;

            tMRD = <7000>;

            tR2R-C2C = <0>;

            tRAS = <23000>;

            tRC = <33750>;

            tRCD = <10000>;

            tRFC = <65000>;

            tRPab = <12000>;

            tRPpb = <12000>;

            tRRD = <6000>;

            tRTP = <3750>;

            tW2W-C2C = <0>;

            tWR = <7500>;

            tWTR = <3750>;

            tXP = <3750>;

            tXSR = <70000>;

        };

    };

Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: LPDDR3 SDRAM compliant to JEDEC JESD209-3



maintainers:

  - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>



properties:

  compatible:

    items:

      - enum:

          - samsung,K3QF2F20DB

      - const: jedec,lpddr3



  '#address-cells':

    const: 1

    deprecated: true



  density:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Density in megabits of SDRAM chip.

    enum:

      - 4096

      - 8192

      - 16384

      - 32768



  io-width:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      IO bus width in bits of SDRAM chip.

    enum:

      - 32

      - 16



  manufacturer-id:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Manufacturer ID value read from Mode Register 5.  The property is

      deprecated, manufacturer should be derived from the compatible.

    deprecated: true



  revision-id:

    $ref: /schemas/types.yaml#/definitions/uint32-array

    minItems: 2

    maxItems: 2

    items:

      maximum: 255

    description: |

      Revision value of SDRAM chip read from Mode Registers 6 and 7.



  '#size-cells':

    const: 0

    deprecated: true



  tCKE-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15

    description: |

      CKE minimum pulse width (HIGH and LOW pulse width) in terms of number

      of clock cycles.



  tCKESR-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15

    description: |

      CKE minimum pulse width during SELF REFRESH (low pulse width during

      SELF REFRESH) in terms of number of clock cycles.



  tDQSCK-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15

    description: |

      DQS output data access time from CK_t/CK_c in terms of number of clock

      cycles.



  tFAW-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 63

    description: |

      Four-bank activate window in terms of number of clock cycles.



  tMRD-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15

    description: |

      Mode register set command delay in terms of number of clock cycles.



  tR2R-C2C-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [0, 1]

    description: |

      Additional READ-to-READ delay in chip-to-chip cases in terms of number

      of clock cycles.



  tRAS-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 63

    description: |

      Row active time in terms of number of clock cycles.



  tRC-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 63

    description: |

      ACTIVATE-to-ACTIVATE command period in terms of number of clock cycles.



  tRCD-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15

    description: |

      RAS-to-CAS delay in terms of number of clock cycles.



  tRFC-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 255

    description: |

      Refresh Cycle time in terms of number of clock cycles.



  tRL-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15

    description: |

     READ data latency in terms of number of clock cycles.



  tRPab-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15

    description: |

      Row precharge time (all banks) in terms of number of clock cycles.



  tRPpb-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15

    description: |

      Row precharge time (single banks) in terms of number of clock cycles.



  tRRD-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15

    description: |

      Active bank A to active bank B in terms of number of clock cycles.



  tRTP-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15

    description: |

      Internal READ to PRECHARGE command delay in terms of number of clock

      cycles.



  tW2W-C2C-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [0, 1]

    description: |

      Additional WRITE-to-WRITE delay in chip-to-chip cases in terms of number

      of clock cycles.



  tWL-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15

    description: |

      WRITE data latency in terms of number of clock cycles.



  tWR-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15

    description: |

      WRITE recovery time in terms of number of clock cycles.



  tWTR-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15

    description: |

      Internal WRITE-to-READ command delay in terms of number of clock cycles.



  tXP-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 255

    description: |

      Exit power-down to next valid command delay in terms of number of clock

      cycles.



  tXSR-min-tck:

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 1023

    description: |

      SELF REFRESH exit to next valid command delay in terms of number of clock

      cycles.



patternProperties:

  "^timings((-[0-9])+|(@[0-9a-f]+))?$":

    $ref: jedec,lpddr3-timings.yaml

    description: |

      The lpddr3 node may have one or more child nodes with timings.

      Each timing node provides AC timing parameters of the device for a given

      speed-bin. The user may provide the timings for as many speed-bins as is

      required.



required:

  - compatible

  - density

  - io-width



additionalProperties: false



examples:

  - |

    lpddr3 {

        compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";

        density = <16384>;

        io-width = <32>;



        tCKE-min-tck = <2>;

        tCKESR-min-tck = <2>;

        tDQSCK-min-tck = <5>;

        tFAW-min-tck = <5>;

        tMRD-min-tck = <5>;

        tR2R-C2C-min-tck = <0>;

        tRAS-min-tck = <5>;

        tRC-min-tck = <6>;

        tRCD-min-tck = <3>;

        tRFC-min-tck = <17>;

        tRL-min-tck = <14>;

        tRPab-min-tck = <2>;

        tRPpb-min-tck = <2>;

        tRRD-min-tck = <2>;

        tRTP-min-tck = <2>;

        tW2W-C2C-min-tck = <0>;

        tWL-min-tck = <8>;

        tWR-min-tck = <7>;

        tWTR-min-tck = <2>;

        tXP-min-tck = <2>;

        tXSR-min-tck = <12>;



        timings {

            compatible = "jedec,lpddr3-timings";

            max-freq = <800000000>;

            min-freq = <100000000>;

            tCKE = <3750>;

            tCKESR = <3750>;

            tFAW = <25000>;

            tMRD = <7000>;

            tR2R-C2C = <0>;

            tRAS = <23000>;

            tRC = <33750>;

            tRCD = <10000>;

            tRFC = <65000>;

            tRPab = <12000>;

            tRPpb = <12000>;

            tRRD = <6000>;

            tRTP = <3750>;

            tW2W-C2C = <0>;

            tWR = <7500>;

            tWTR = <3750>;

            tXP = <3750>;

            tXSR = <70000>;

        };

    };

Documentation/devicetree/bindings/memory-controllers/ddr/lpddr2-timings.txt

deleted100644 → 0
+0 −52
Original line number Original line Diff line number Diff line 
* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin



Required properties:

- compatible : Should be "jedec,lpddr2-timings"

- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>

- max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>



Optional properties:



The following properties represent AC timing parameters from the memory

data-sheet of the device for a given speed-bin. All these properties are

of type <u32> and the default unit is ps (pico seconds). Parameters with

a different unit have a suffix indicating the unit such as 'tRAS-max-ns'

- tRCD

- tWR

- tRAS-min

- tRRD

- tWTR

- tXP

- tRTP

- tDQSCK-max

- tFAW

- tZQCS

- tZQinit

- tRPab

- tZQCL

- tCKESR

- tRAS-max-ns

- tDQSCK-max-derated



Example:



timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {

	compatible	= "jedec,lpddr2-timings";

	min-freq	= <10000000>;

	max-freq	= <400000000>;

	tRPab		= <21000>;

	tRCD		= <18000>;

	tWR		= <15000>;

	tRAS-min	= <42000>;

	tRRD		= <10000>;

	tWTR		= <7500>;

	tXP		= <7500>;

	tRTP		= <7500>;

	tCKESR		= <15000>;

	tDQSCK-max	= <5500>;

	tFAW		= <50000>;

	tZQCS		= <90000>;

	tZQCL		= <360000>;

	tZQinit		= <1000000>;

	tRAS-max-ns	= <70000>;

};