Commit b8b9ffce authored by Dan Williams's avatar Dan Williams
Browse files

Merge branch 'for-6.3/cxl-ram-region' into cxl/next 

Include the support for enumerating and provisioning ram regions for
v6.3. This also include a default policy change for ram / volatile
device-dax instances to assign them to the dax_kmem driver by default.
parents dfd423e0 09d09e04

Documentation/ABI/testing/sysfs-bus-cxl

+38 −26
Original line number Diff line number Diff line
@@ -198,7 +198,7 @@ Description: 


What:		/sys/bus/cxl/devices/endpointX/CDAT

Date:		July, 2022

KernelVersion:	v5.20

KernelVersion:	v6.0

Contact:	linux-cxl@vger.kernel.org

Description:

		(RO) If this sysfs entry is not present no DOE mailbox was
@@ -209,7 +209,7 @@ Description: 


What:		/sys/bus/cxl/devices/decoderX.Y/mode

Date:		May, 2022

KernelVersion:	v5.20

KernelVersion:	v6.0

Contact:	linux-cxl@vger.kernel.org

Description:

		(RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
@@ -229,7 +229,7 @@ Description: 


What:		/sys/bus/cxl/devices/decoderX.Y/dpa_resource

Date:		May, 2022

KernelVersion:	v5.20

KernelVersion:	v6.0

Contact:	linux-cxl@vger.kernel.org

Description:

		(RO) When a CXL decoder is of devtype "cxl_decoder_endpoint",
@@ -240,7 +240,7 @@ Description: 


What:		/sys/bus/cxl/devices/decoderX.Y/dpa_size

Date:		May, 2022

KernelVersion:	v5.20

KernelVersion:	v6.0

Contact:	linux-cxl@vger.kernel.org

Description:

		(RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
@@ -260,7 +260,7 @@ Description: 


What:		/sys/bus/cxl/devices/decoderX.Y/interleave_ways

Date:		May, 2022

KernelVersion:	v5.20

KernelVersion:	v6.0

Contact:	linux-cxl@vger.kernel.org

Description:

		(RO) The number of targets across which this decoder's host
@@ -275,7 +275,7 @@ Description: 


What:		/sys/bus/cxl/devices/decoderX.Y/interleave_granularity

Date:		May, 2022

KernelVersion:	v5.20

KernelVersion:	v6.0

Contact:	linux-cxl@vger.kernel.org

Description:

		(RO) The number of consecutive bytes of host physical address
@@ -285,25 +285,25 @@ Description: 
		interleave_granularity).





What:		/sys/bus/cxl/devices/decoderX.Y/create_pmem_region

Date:		May, 2022

KernelVersion:	v5.20

What:		/sys/bus/cxl/devices/decoderX.Y/create_{pmem,ram}_region

Date:		May, 2022, January, 2023

KernelVersion:	v6.0 (pmem), v6.3 (ram)

Contact:	linux-cxl@vger.kernel.org

Description:

		(RW) Write a string in the form 'regionZ' to start the process

		of defining a new persistent memory region (interleave-set)

		within the decode range bounded by root decoder 'decoderX.Y'.

		The value written must match the current value returned from

		reading this attribute. An atomic compare exchange operation is

		done on write to assign the requested id to a region and

		allocate the region-id for the next creation attempt. EBUSY is

		returned if the region name written does not match the current

		cached value.

		of defining a new persistent, or volatile memory region

		(interleave-set) within the decode range bounded by root decoder

		'decoderX.Y'. The value written must match the current value

		returned from reading this attribute. An atomic compare exchange

		operation is done on write to assign the requested id to a

		region and allocate the region-id for the next creation attempt.

		EBUSY is returned if the region name written does not match the

		current cached value.





What:		/sys/bus/cxl/devices/decoderX.Y/delete_region

Date:		May, 2022

KernelVersion:	v5.20

KernelVersion:	v6.0

Contact:	linux-cxl@vger.kernel.org

Description:

		(WO) Write a string in the form 'regionZ' to delete that region,
@@ -312,17 +312,18 @@ Description: 


What:		/sys/bus/cxl/devices/regionZ/uuid

Date:		May, 2022

KernelVersion:	v5.20

KernelVersion:	v6.0

Contact:	linux-cxl@vger.kernel.org

Description:

		(RW) Write a unique identifier for the region. This field must

		be set for persistent regions and it must not conflict with the

		UUID of another region.

		UUID of another region. For volatile ram regions this

		attribute is a read-only empty string.





What:		/sys/bus/cxl/devices/regionZ/interleave_granularity

Date:		May, 2022

KernelVersion:	v5.20

KernelVersion:	v6.0

Contact:	linux-cxl@vger.kernel.org

Description:

		(RW) Set the number of consecutive bytes each device in the
@@ -333,7 +334,7 @@ Description: 


What:		/sys/bus/cxl/devices/regionZ/interleave_ways

Date:		May, 2022

KernelVersion:	v5.20

KernelVersion:	v6.0

Contact:	linux-cxl@vger.kernel.org

Description:

		(RW) Configures the number of devices participating in the
@@ -343,7 +344,7 @@ Description: 


What:		/sys/bus/cxl/devices/regionZ/size

Date:		May, 2022

KernelVersion:	v5.20

KernelVersion:	v6.0

Contact:	linux-cxl@vger.kernel.org

Description:

		(RW) System physical address space to be consumed by the region.
@@ -358,9 +359,20 @@ Description: 
		results in the same address being allocated.





What:		/sys/bus/cxl/devices/regionZ/mode

Date:		January, 2023

KernelVersion:	v6.3

Contact:	linux-cxl@vger.kernel.org

Description:

		(RO) The mode of a region is established at region creation time

		and dictates the mode of the endpoint decoder that comprise the

		region. For more details on the possible modes see

		/sys/bus/cxl/devices/decoderX.Y/mode





What:		/sys/bus/cxl/devices/regionZ/resource

Date:		May, 2022

KernelVersion:	v5.20

KernelVersion:	v6.0

Contact:	linux-cxl@vger.kernel.org

Description:

		(RO) A region is a contiguous partition of a CXL root decoder
@@ -372,7 +384,7 @@ Description: 


What:		/sys/bus/cxl/devices/regionZ/target[0..N]

Date:		May, 2022

KernelVersion:	v5.20

KernelVersion:	v6.0

Contact:	linux-cxl@vger.kernel.org

Description:

		(RW) Write an endpoint decoder object name to 'targetX' where X
@@ -391,7 +403,7 @@ Description: 


What:		/sys/bus/cxl/devices/regionZ/commit

Date:		May, 2022

KernelVersion:	v5.20

KernelVersion:	v6.0

Contact:	linux-cxl@vger.kernel.org

Description:

		(RW) Write a boolean 'true' string value to this attribute to

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -6034,6 +6034,7 @@ M: Dan Williams <dan.j.williams@intel.com> 
M:	Vishal Verma <vishal.l.verma@intel.com>

M:	Dave Jiang <dave.jiang@intel.com>

L:	nvdimm@lists.linux.dev

L:	linux-cxl@vger.kernel.org

S:	Supported

F:	drivers/dax/
































drivers/acpi/numa/hmat.c



+2
−2






























Original line number
Diff line number
Diff line







@@ -718,7 +718,7 @@ static void hmat_register_target_devices(struct memory_target *target)







	for (res = target->memregions.child; res; res = res->sibling) {









		int target_nid = pxm_to_node(target->memory_pxm);



















		hmem_register_device(target_nid, res);









		hmem_register_resource(target_nid, res);









	}









}


















@@ -869,4 +869,4 @@ static __init int hmat_init(void)







	acpi_put_table(tbl);









	return 0;









}









device_initcall(hmat_init);








subsys_initcall(hmat_init);
























drivers/cxl/Kconfig



+11
−1






























Original line number
Diff line number
Diff line







@@ -104,12 +104,22 @@ config CXL_SUSPEND







	depends on SUSPEND && CXL_MEM



















config CXL_REGION









	bool









	bool "CXL: Region Support"









	default CXL_BUS









	# For MAX_PHYSMEM_BITS









	depends on SPARSEMEM









	select MEMREGION









	select GET_FREE_REGION









	help









	  Enable the CXL core to enumerate and provision CXL regions. A CXL









	  region is defined by one or more CXL expanders that decode a given









	  system-physical address range. For CXL regions established by









	  platform-firmware this option enables memory error handling to









	  identify the devices participating in a given interleaved memory









	  range. Otherwise, platform-firmware managed CXL is enabled by being









	  placed in the system address map and does not need a driver.



















	  If unsure say 'y'



















config CXL_REGION_INVALIDATION_TEST









	bool "CXL: Region Cache Management Bypass (TEST)"
































drivers/cxl/acpi.c



+2
−1






























Original line number
Diff line number
Diff line







@@ -731,7 +731,8 @@ static void __exit cxl_acpi_exit(void)







	cxl_bus_drain();









}



















module_init(cxl_acpi_init);









/* load before dax_hmem sees 'Soft Reserved' CXL ranges */









subsys_initcall(cxl_acpi_init);









module_exit(cxl_acpi_exit);









MODULE_LICENSE("GPL v2");









MODULE_IMPORT_NS(CXL);