Commit b89e9eb6 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/powerplay: optimize amdgpu_dpm_set_clockgating_by_smu() implementation 



Cover the implementation details from outside(of power part).

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Acked-by: default avatarNirmoy Das <nirmoy.das@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 171090db

drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c

+15 −0
Original line number Diff line number Diff line
@@ -1232,3 +1232,18 @@ int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) 


	return ret;

}



int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev,

				      uint32_t msg_id)

{

	void *pp_handle = adev->powerplay.pp_handle;

	const struct amd_pm_funcs *pp_funcs =

			adev->powerplay.pp_funcs;

	int ret = 0;



	if (pp_funcs && pp_funcs->set_clockgating_by_smu)

		ret = pp_funcs->set_clockgating_by_smu(pp_handle,

						       msg_id);



	return ret;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h

+3 −4
Original line number Diff line number Diff line
@@ -341,10 +341,6 @@ enum amdgpu_pcie_gen { 
		((adev)->powerplay.pp_funcs->reset_power_profile_state(\

			(adev)->powerplay.pp_handle, request))



#define amdgpu_dpm_set_clockgating_by_smu(adev, msg_id) \

		((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\

			(adev)->powerplay.pp_handle, msg_id))



#define amdgpu_dpm_get_power_profile_mode(adev, buf) \

		((adev)->powerplay.pp_funcs->get_power_profile_mode(\

			(adev)->powerplay.pp_handle, buf))
@@ -546,4 +542,7 @@ int amdgpu_dpm_allow_xgmi_power_down(struct amdgpu_device *adev, bool en); 


int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev);



int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev,

				      uint32_t msg_id);



#endif

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+7 −14
Original line number Diff line number Diff line
@@ -5880,7 +5880,6 @@ static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev, 
				PP_BLOCK_GFX_CG,

				pp_support_state,

				pp_state);

		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)

		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);

	}
@@ -5902,7 +5901,6 @@ static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev, 
				PP_BLOCK_GFX_MG,

				pp_support_state,

				pp_state);

		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)

		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);

	}
@@ -5932,7 +5930,6 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev, 
				PP_BLOCK_GFX_CG,

				pp_support_state,

				pp_state);

		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)

		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);

	}
@@ -5952,7 +5949,6 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev, 
				PP_BLOCK_GFX_3D,

				pp_support_state,

				pp_state);

		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)

		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);

	}
@@ -5974,7 +5970,6 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev, 
				PP_BLOCK_GFX_MG,

				pp_support_state,

				pp_state);

		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)

		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);

	}
@@ -5990,7 +5985,6 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev, 
				PP_BLOCK_GFX_RLC,

				pp_support_state,

				pp_state);

		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)

		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);

	}
@@ -6005,7 +5999,6 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev, 
			PP_BLOCK_GFX_CP,

			pp_support_state,

			pp_state);

		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)

		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);

	}

drivers/gpu/drm/amd/amdgpu/vi.c

+7 −14
Original line number Diff line number Diff line
@@ -1507,7 +1507,6 @@ static int vi_common_set_clockgating_state_by_smu(void *handle, 
			       PP_BLOCK_SYS_MC,

			       pp_support_state,

			       pp_state);

		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)

		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);

	}
@@ -1526,7 +1525,6 @@ static int vi_common_set_clockgating_state_by_smu(void *handle, 
			       PP_BLOCK_SYS_SDMA,

			       pp_support_state,

			       pp_state);

		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)

		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);

	}
@@ -1545,7 +1543,6 @@ static int vi_common_set_clockgating_state_by_smu(void *handle, 
			       PP_BLOCK_SYS_HDP,

			       pp_support_state,

			       pp_state);

		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)

		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);

	}
@@ -1560,7 +1557,6 @@ static int vi_common_set_clockgating_state_by_smu(void *handle, 
			       PP_BLOCK_SYS_BIF,

			       PP_STATE_SUPPORT_LS,

			        pp_state);

		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)

		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);

	}

	if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {
@@ -1573,7 +1569,6 @@ static int vi_common_set_clockgating_state_by_smu(void *handle, 
			       PP_BLOCK_SYS_BIF,

			       PP_STATE_SUPPORT_CG,

			       pp_state);

		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)

		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);

	}
@@ -1588,7 +1583,6 @@ static int vi_common_set_clockgating_state_by_smu(void *handle, 
			       PP_BLOCK_SYS_DRM,

			       PP_STATE_SUPPORT_LS,

			       pp_state);

		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)

		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);

	}
@@ -1603,7 +1597,6 @@ static int vi_common_set_clockgating_state_by_smu(void *handle, 
			       PP_BLOCK_SYS_ROM,

			       PP_STATE_SUPPORT_CG,

			       pp_state);

		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)

		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);

	}

	return 0;