Unverified Commit b863a748 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!10796 Revert "ARM: spectre-v2: turn off the mitigation via boot cmdline param" 

Merge Pull Request from: @ci-robot 
 
PR sync from: felix <fuzhen5@huawei.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/77JNV7HO4HIY7ONMCLG2A57ZJODMFLUU/ 
 
https://gitee.com/src-openeuler/kernel/issues/IAI881 
 
Link:https://gitee.com/openeuler/kernel/pulls/10796

 

Reviewed-by: default avatarZhang Jianhua <chris.zjh@huawei.com>
Signed-off-by: default avatarZhang Peng <zhangpeng362@huawei.com>
parents 02036602 d2970282

arch/arm/include/asm/system_misc.h

+0 −1
Original line number Diff line number Diff line
@@ -36,7 +36,6 @@ static inline void harden_branch_predictor(void) 
#define UDBG_BUS	(1 << 4)



extern unsigned int user_debug;

extern int nospectre_v2;



#endif /* !__ASSEMBLY__ */

arch/arm/mm/proc-v7-bugs.c

+0 −18
Original line number Diff line number Diff line
@@ -9,19 +9,6 @@ 
#include <asm/spectre.h>

#include <asm/system_misc.h>



/*

 * 32-bit ARM spectre hardening, enabled by default, can be disabled via boot

 * cmdline param 'nospectre_v2' to avoid performance regression.

 */

int nospectre_v2 __read_mostly;



static int __init nospectre_v2_setup(char *str)

{

	nospectre_v2 = 1;

	return 0;

}

early_param("nospectre_v2", nospectre_v2_setup);



#ifdef CONFIG_ARM_PSCI

static int __maybe_unused spectre_v2_get_cpu_fw_mitigation_state(void)

{
@@ -131,11 +118,6 @@ static void cpu_v7_spectre_v2_init(void) 
{

	unsigned int state, method = 0;



	if (nospectre_v2) {

		pr_info_once("Spectre v2: hardening is disabled\n");

		return;

	}



	switch (read_cpuid_part()) {

	case ARM_CPU_PART_CORTEX_A8:

	case ARM_CPU_PART_CORTEX_A9:

arch/arm/mm/proc-v7.S

+0 −9
Original line number Diff line number Diff line
@@ -113,23 +113,14 @@ ENTRY(cpu_v7_hvc_switch_mm) 
	b	cpu_v7_switch_mm

ENDPROC(cpu_v7_hvc_switch_mm)

#endif



ENTRY(cpu_v7_iciallu_switch_mm)

	ldr_l r3, nospectre_v2

	cmp r3, #1

	beq 1f

	mov	r3, #0

	mcr	p15, 0, r3, c7, c5, 0		@ ICIALLU

1:

	b	cpu_v7_switch_mm

ENDPROC(cpu_v7_iciallu_switch_mm)

ENTRY(cpu_v7_bpiall_switch_mm)

	ldr_l r3, nospectre_v2

	cmp r3, #1

	beq 1f

	mov	r3, #0

	mcr	p15, 0, r3, c7, c5, 6		@ flush BTAC/BTB

1:

	b	cpu_v7_switch_mm

ENDPROC(cpu_v7_bpiall_switch_mm)