Commit b857e147 authored by James Zhu's avatar James Zhu Committed by Alex Deucher
Browse files

drm/amdgpu: move out asic specific definition from common header 



Move out asic specific definition from common header.

Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarLeo Liu <leo.liu@amd.com>
Reviewed-by: default avatarSonny Jiang <sonny.jiang@amd.com>
Signed-off-by: default avatarJames Zhu <James.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1218a2e3

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

+0 −2
Original line number Diff line number Diff line
@@ -65,8 +65,6 @@ 
#define VCN_ENC_CMD_REG_WRITE		0x0000000b

#define VCN_ENC_CMD_REG_WAIT		0x0000000c



#define VCN_VID_SOC_ADDRESS_2_0 	0x1fa00

#define VCN1_VID_SOC_ADDRESS_3_0 	0x48200

#define VCN_AON_SOC_ADDRESS_2_0 	0x1f800

#define VCN1_AON_SOC_ADDRESS_3_0 	0x48000

#define VCN_VID_IP_ADDRESS_2_0		0x0

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

+3 −0
Original line number Diff line number Diff line
@@ -37,6 +37,9 @@ 
#include "vcn/vcn_2_0_0_sh_mask.h"

#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"



#define VCN_VID_SOC_ADDRESS_2_0					0x1fa00

#define VCN1_VID_SOC_ADDRESS_3_0				0x48200



#define mmUVD_CONTEXT_ID_INTERNAL_OFFSET			0x1fd

#define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET			0x503

#define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET			0x504

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

+3 −0
Original line number Diff line number Diff line
@@ -37,6 +37,9 @@ 
#include "vcn/vcn_2_5_sh_mask.h"

#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"



#define VCN_VID_SOC_ADDRESS_2_0					0x1fa00

#define VCN1_VID_SOC_ADDRESS_3_0				0x48200



#define mmUVD_CONTEXT_ID_INTERNAL_OFFSET			0x27

#define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET			0x0f

#define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET			0x10

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

+3 −0
Original line number Diff line number Diff line
@@ -37,6 +37,9 @@ 


#include <drm/drm_drv.h>



#define VCN_VID_SOC_ADDRESS_2_0					0x1fa00

#define VCN1_VID_SOC_ADDRESS_3_0				0x48200



#define mmUVD_CONTEXT_ID_INTERNAL_OFFSET			0x27

#define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET			0x0f

#define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET			0x10