Unverified Commit b83e5eba authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!15272 [Intel-SIG] 5.10-x86/cpu: Clearwater Forest new model and ISAs support. 

Merge Pull Request from: @quanxianwang 
 
Content:
1. x86: KVM: Advertise CPUIDs for new instructions in Clearwater Forest
2. x86/cpu: Add model number for Intel Clearwater Forest processor

Intel-Kernel Issue:
#IBPCSD:CWF-model and ISA kernel support

Test:
Boot test on CWF simics server

Known issue:
N/A

Default config change:
N/A
 
 
Link:https://gitee.com/openeuler/kernel/pulls/15272

 

Reviewed-by: default avatarJason Zeng <jason.zeng@intel.com>
Reviewed-by: default avatarLi Nan <linan122@huawei.com>
Signed-off-by: default avatarLi Nan <linan122@huawei.com>
parents a7973281 f153d353

arch/x86/include/asm/cpufeatures.h

+3 −0
Original line number Diff line number Diff line
@@ -335,6 +335,9 @@ 
#define X86_FEATURE_ZEN1		(11*32+31) /* "" CPU based on Zen1 microarchitecture */



/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */

#define X86_FEATURE_SHA512		(12*32+ 0) /* SHA512 instructions */

#define X86_FEATURE_SM3			(12*32+ 1) /* SM3 instructions */

#define X86_FEATURE_SM4			(12*32+ 2) /* SM4 instructions */

#define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */

#define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */

#define X86_FEATURE_CMPCCXADD           (12*32+ 7) /* "" CMPccXADD instructions */

arch/x86/include/asm/intel-family.h

+2 −0
Original line number Diff line number Diff line
@@ -152,6 +152,8 @@ 
#define INTEL_FAM6_ATOM_CRESTMONT_X	0xAF /* Sierra Forest */

#define INTEL_FAM6_ATOM_CRESTMONT	0xB6 /* Grand Ridge */



#define INTEL_FAM6_ATOM_DARKMONT_X	0xDD /* Clearwater Forest */



/* Xeon Phi */



#define INTEL_FAM6_XEON_PHI_KNL		0x57 /* Knights Landing */

arch/x86/kvm/cpuid.c

+5 −3
Original line number Diff line number Diff line
@@ -517,12 +517,14 @@ void kvm_set_cpu_caps(void) 
		kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD);



	kvm_cpu_cap_mask(CPUID_7_1_EAX,

		F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) | F(AMX_FP16) |

		F(AVX_IFMA) | F(FZRM) | F(FSRS) | F(FSRC)

		F(SHA512) | F(SM3) | F(SM4) | F(AVX_VNNI) | F(AVX512_BF16) |

		F(CMPCCXADD) | F(FZRM) | F(FSRS) | F(FSRC) | F(AMX_FP16) |

		F(AVX_IFMA)

	);



	kvm_cpu_cap_init_kvm_defined(CPUID_7_1_EDX,

		F(AVX_VNNI_INT8) | F(AVX_NE_CONVERT) | F(PREFETCHITI)

		F(AVX_VNNI_INT8) | F(AVX_NE_CONVERT) | F(AVX_VNNI_INT16) |

		F(PREFETCHITI)

	);



	kvm_cpu_cap_mask(CPUID_D_1_EAX,

arch/x86/kvm/cpuid.h

+1 −0
Original line number Diff line number Diff line
@@ -101,6 +101,7 @@ static inline bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa) 
/* Intel-defined sub-features, CPUID level 0x00000007:1 (EDX) */

#define X86_FEATURE_AVX_VNNI_INT8       KVM_X86_FEATURE(CPUID_7_1_EDX, 4)

#define X86_FEATURE_AVX_NE_CONVERT      KVM_X86_FEATURE(CPUID_7_1_EDX, 5)

#define X86_FEATURE_AVX_VNNI_INT16      KVM_X86_FEATURE(CPUID_7_1_EDX, 10)

#define X86_FEATURE_PREFETCHITI         KVM_X86_FEATURE(CPUID_7_1_EDX, 14)



struct cpuid_reg {