Commit b814eda9 authored by Lucas Stach's avatar Lucas Stach Committed by Shawn Guo
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soc: imx: imx8mp-blk-ctrl: enable global pixclk with HDMI_TX_PHY PD



NXP internal information shows that the PHY refclk is gated by the
GLOBAL_TX_PIX_CLK_EN bit, so to allow the PHY PLL to lock without the
LCDIF being already active, tie this bit to the HDMI_TX_PHY power
domain.

Fixes: e3442022 ("soc: imx: add i.MX8MP HDMI blk-ctrl")
Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 1b929c02
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+4 −2
Original line number Diff line number Diff line
@@ -212,7 +212,7 @@ static void imx8mp_hdmi_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
		break;
	case IMX8MP_HDMIBLK_PD_LCDIF:
		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
				BIT(7) | BIT(16) | BIT(17) | BIT(18) |
				BIT(16) | BIT(17) | BIT(18) |
				BIT(19) | BIT(20));
		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));
		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
@@ -241,6 +241,7 @@ static void imx8mp_hdmi_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
		regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(1));
		break;
	case IMX8MP_HDMIBLK_PD_HDMI_TX_PHY:
		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(7));
		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
		regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
@@ -270,7 +271,7 @@ static void imx8mp_hdmi_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
				  BIT(4) | BIT(5) | BIT(6));
		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));
		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
				  BIT(7) | BIT(16) | BIT(17) | BIT(18) |
				  BIT(16) | BIT(17) | BIT(18) |
				  BIT(19) | BIT(20));
		break;
	case IMX8MP_HDMIBLK_PD_PAI:
@@ -298,6 +299,7 @@ static void imx8mp_hdmi_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
	case IMX8MP_HDMIBLK_PD_HDMI_TX_PHY:
		regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(7));
		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
		break;
	case IMX8MP_HDMIBLK_PD_HDCP: